BMISx-Bus Master IDE Status Register I/O | Intel 460GX specification

IDE Configuration

Bit	Description

7:4	Reserved.

3	Bus Master Read/Write Control (RWCON). 0=Reads; 1=Writes. This bit must NOT be changed
	when the bus master Function is active.
	While a synchronous DMA transfer is in progress, this bit will be READ ONLY. The bit will return to
	read/write once the synchronous DMA transfer has been completed or halted.

2:1	Reserved.

0	Start/Stop Bus Master (SSBM). 1=Start; 0=Stop. When this bit is set to 1, bus master operation
	starts. The controller transfers data between the IDE device and memory only while this bit is set.
	Master operation can be stopped by writing a 0 to this bit. This results in all state information being
	lost (i.e. master mode operation cannot be stopped and then resumed).
	If this bit is set to 0 while bus master operation is still active (i.e. Bit 0=1 in the Bus Master IDE Status
	Register for that IDE channel) and the drive has not yet finished its data transfer (bit 2=0 in the
	channel’s Bus Master IDE Status Register), the bus master command is aborted and data
	transferred from the drive may be discarded by the IFB rather than being written to system memory.
	This bit is intended to be set to 0 after the data transfer is completed, as indicated by either bit 0 or
	bit 2 being set in the IDE Channel’s Bus Master IDE Status Register.

12.3.2BMISx–Bus Master IDE Status Register (I/O)

Address Offset:	Primary Channel–Base + 02h; Secondary Channel–Base + 0Ah
Default Value:	00h
Attribute:	Read/Write Clear

This register provides status information about the IDE device and state of the IDE DMA transfer.

Bit	Description

7	Reserved. This bit is hardwired to 0.

6	Drive 1 DMA Capable (DMA1CAP)–R/W.1=Drive 1 is capable of DMA transfers. This bit is a
	software controlled status bit that indicates IDE DMA device capability and does not affect
	hardware operation.

5	Drive 0 DMA Capable (DMA0CAP)–R/W.1=Drive 0 is capable of DMA transfers. This bit is a
	software controlled status bit that indicates IDE DMA device capability and does not affect
	hardware operation.

4:3	Reserved.

2	IDE Interrupt Status (IDEINTS)–R/WC.This bit, when set to a 1, indicates when an IDE device
	has asserted its interrupt line. When bit 2=1, all read data from the IDE device has been
	transferred to main memory and all write data has been transferred to the IDE device. Software
	sets this bit to a 0 by writing a 1 to it. IRQ14 is used for the primary channel and IRQ15 is used
	for the secondary channel. Note that, if the interrupt status bit is set to a 0 by writing a 1 to this
	bit while the interrupt line is still at the active level, this bit remains 0 until another assertion edge
	is detected on the interrupt line.

1	IDE DMA Error–R/WC.This bit is set to 1 when the IFB encounters a target abort or master
	abort while transferring data on the PCI Bus. Software sets this bit to a 0 by writing a 1 to it.

0	Bus Master IDE Active (BMIDEA)–RO.The IFB sets this bit to 1 when bit 0 in the BMICx
	Register is set to 1. The IFB sets this bit to 0 when the last transfer for a region is performed
	(where EOT for that region is set in the region descriptor). The IFB also sets this bit to 0 when
	bit 0 of the BMICx Register is set to 0. When this bit is read as a zero, all data transferred from
	the drive during the previous bus master command is visible in system memory, unless the bus
	master command was aborted.

12-10

Intel® 460GX Chipset Software Developer’s Manual

Image 242

Intel 460GX manual BMISx-Bus Master IDE Status Register I/O

Contents

Intel 460GX Chipset System Software Developer’s Manual Intel 460GX Chipset System Software Developer’s Manual Contents Coherency 10.1 Latency 10-1 11-8 13.2.4 Figures Tables 12-11 Introduction System Overview Name Function Component OverviewIntel 460GX Chipset Components Product Features Itanium Processor System Bus Support I/O Support PXB FeaturesDram Interface Support RAS Features GXB Features 1 I/O & Firmware Bridge IFB Other Platform ComponentsReference Documents Programmable Interrupt Device PID Revision History Date Description June Initial release Introduction Access Mechanism Register Descriptions Device Mapping on Bus CBN Access RestrictionsPartitioning Device Reserved Bits Defined in Registers Default Upon ResetRegister Attributes Reserved or Undefined Register Locations Consistency Configaddress Configuration Address RegisterI/O Mapped Registers Gart Programming Region 1 SAC Error Handling RegistersConfigdata Configuration Data Register 1.1 1.3 Bits Description Disable1.2 Valid Ferrsac First Error Status Register Nerrsac All Error Status Register Saferr System Address on First Error Biuitid BIU Itid Register Biudata BIU Data Register Address bits 2.2 SEC0ECCFERR ECC on First Memory Card B SEC 2 SDC2.1 SEC0DFERR Data on First Memory Card B SEC 2.3 SEC0TXINFOFERR Txinfo on First Memory Card B SEC 2.6 DED0TXINFOFERR Txinfo on First Memory Card B DED 2.4 DED0DFERR Data on First Memory Card B DED2.5 DED0ECCFERR ECC on First Memory Card B DED 2.7 SEC1DFERR Data on First Memory Card a SEC 2.10 DED1DFERR Data on First Memory Card a DED 2.8 SEC1ECCFERR ECC on First Memory Card a SEC2.9 SEC1TXINFOFERR Txinfo on First Memory Card a SEC 2.12 DED1TXINFOFERR Txinfo on First Memory Card a DED Sdcferr First Error Status Register2.11 DED1ECCFERR ECC on First Memory Card a DED 15 ’Forward’ Underflow Card B Right Stack Error FR0 22 ’Forward’ Underflow Card a Right Stack Error FR121 ’Forward’ Underflow Card a Left Stack Error FL1 14 ’Forward’ Underflow Card B Left Stack Error FL0 Pitidferr Data on First Pitid Parity Error Sdcnerr SDC Next Error Status RegisterPcmdferr Command on First Pcmd Parity Error ECCMSK0 ECC Mask Register Card B Sdcrspferr Response on First Sdcrsp ErrorDpbrleferr Private Data Bus Receive Length Error Eccmskf ECC Mask Register ParMskP PB Parity Mask and IB Correction Enable RegisterECCMSK1 ECC Mask Register Card a Pvdtxinfoferr Txinfo on First PVD Parity Error Pvddferr Data on First PVD Parity ErrorPvdparferr Parity on First PVD Parity Error Secftxinfoferr Txinfo on First System Bus SEC Secfdferr Data on First System Bus SECSecfeccferr ECC on First System Bus SEC Dedfdferr Data on First System Bus DED 3 MAC Ferrmac First Error Status RegisterQue-Overflow Error Dedfeccferr ECC on First System Bus DED 4 PXB Cmndferr Command on First ErrorErrsts Error Status Register Errcmd Error Command Register 5.1 Ferragp First Error Status Register for AGP5 GXB Ferrpci Ferrgart First Error Status Register for Gart Nerragp Next Errors Status Register for AGP Nerrgart Pacerr PCI Address & Cmd First ErrorPderr PCI Data First Error 6 WXB Nepci Register Records an PCI Bus Error FlagFepci Register Records an PCI Bus Error Flag Bits Description Intrq Asserted Flag Fepci PCI Bus First Error Status Register Nepci PCI Bus Next Error Status Register Performance Monitor Registers Fepcial PCI First Error Address/Command LogFepcidl PCI First Error Data Log 6764 C/BE30 6332 AD6332 310 AD310 Length Encodings OverflowCount Value Dmask Encodings Umask Encodings Event Select Reload Control Disable SourceEnable Source 2 SDC FSBDPMD1,0 System Bus Performance Monitor Data Registers 3.2 PMR10 Performance Monitoring Response 3 PXB3.1 PMD10 Performance Monitoring Data Register Count Data Cycles Reload Mode3.3 PME10 Performance Monitoring Event Selection Initiating Agent Selection 4 GXB AGPPMD0,1 AGP Performance Monitor Data Registers Event 1 Input Pcipmd PCI Performance Monitor Data RegistersPercon Performance Monitor Control Register Pipe or Sideband Request Mask AGPPMC0,1 AGP Performance Monitor Configuration RegisterEvent 0 Input Initiating Agent Pcipmc PCI Performance Monitor Configuration RegisterEVENT1 Count Enable Disable Source Data Transfer and Transaction Qualifier PCIWXBPMC0 PCI Performance Monitor Configuration Register5 WXB Issuing Agent Qualifier Xtprs External Task Priority Registers PCIWXBPMC1 PCI Performance Monitor Configuration RegisterInterrupt Related Registers 2.1 I/O Register Select Register FEC00000h Address Name Access Default ValuePID PCI Memory-mapped Registers Memory-Mapped Register Summary XAPIC EOI Register FEC00040h PID Indirect Access Registers2.2 I/O Window Register FEC00010h I/O Window Register Format RTE Offset Name Access Default Value3.1 I/O xAPIC ID Register 00h Memory-mapped Register Summary Cont’d I/O Apic ID Register Format 3.2 I/O xAPIC Version Register 01h3.3 I/O xAPIC Arbitration ID Register 02h I/O xAPIC Version Register Format I/O xAPIC Arbitration ID Register Format Bits Sapic Mode Apic Mode Description Name3.4 I/O xAPIC RTE 10h-8Fh 10. I/O xAPIC RTE Format Sapic Mode Apic Mode Description Name 10. I/O xAPIC RTE Format Cont’d Destination Vector Processor Coherency System ArchitectureCoherency AGP Coherency OrderingPCI Coherency Arbitration for Inbound Transactions WXB ArbitrationWXB Arbitration at the PCI Bus Processor Locks Big-endian SupportIndivisible Operations Arbitration for Outbound Transactions Atomic Reads Inbound PCI LocksAtomic Writes Locks with AGP Non-coherent Traffic Interrupt Delivery WXB PCI Hot-Plug Support Slot Power-up and Enable Slot Power-down and Disable System Architecture Compatibility Region System Address MapMemory Map System Firmware System Memory Address Space Low Extended Memory Region Medium Extended Memory Region Variable GAP High Extended Memory above 4GRe-mapped Memory Areas I/O Address Map Itanium Processor and Chipset-specific Memory Space System I/O Address Space Devices View of the System Memory Map High PXB must ignore GXB must BINIT# after Gart Address Range Outbound Inbound Dest. Decision Legal and Illegal Address DispositionAddress Disposition Above TOM Address Disposition Cont’dMain memory if present above 4 GB Binit System Address Map Organization General Memory CharacteristicsMemory Subsystem System Maximum Memory Configuration Using Two Cards Dimm Types Minimum/Maximum Memory Size per ConfigurationTechnology & Configuration Size Double Number Memory Size Interleaving/Configurations Address Interleaving Bandwidth Summary of Configuration RulesNon-uniform Memory Configurations Auto Detection Supporting FeaturesMemory Subsystem Clocking Removing a Bad Row Scrubbing Time Hardware InitializationMemory Scrubbing Memory Size Time to Scrub Memory Subsystem System Bus Data Integrity and Error HandlingIntegrity PCI Buses DramExpander Buses 5 AGP Data Poisoning Usage of First-error and Next-errorMemory ECC Routing INTREQ# Masked BitsBERR#/BINIT# Generation XBINIT# SAC/SDC ErrorsData ECC or Parity Errors XSERR# System Bus Errors SAC to SDC Interface Errors SAC to MAC Interface Errors 5 SDC/Memory Card Interface Errors SDC Internal Errors Error Determination6 SDC/System Bus Errors SAC Address on an Error SDC Logging Registers Special Notes on Usage of SECTID, DEDTID, Fsetid Registers 1 SAC/SDC Error Clearing Clearing ErrorsMultiple Errors SDC Multiple Errors ERR ERR Error Anomalies SAC Multiple ErrorsSingle Errors with Multiple Reporting Data Flow Errors SAC Error Flow on Data Error Conditions Table of Errors System Bus ADD/CMND Error CasesSAC to SDC Interface Errors Error Cases Cont’d Internal SDC Error PXB Errors Detected as PCI Master PXB as Master PCI IntegrityPCI Bus Monitoring Master Abort PXB as Target Target Abort GXB Error FlowTarget Retry GXB Error Signals GXB Errors Gart Interface Errors Multiple Errors GXB Error Flow Integrity WXB Data Integrity and Error HandlingUsage of First Error and Next Error Registers Data Parity Poisoning Supported Error Escalation to XBINIT#a Error Mask BitsError Steering/Signaling Abbreviation Error SERR# Generation Supported Error Escalation to SERROUT#aSupported Error Escalation to PA/BINTRQ# Escalation XBINIT# Generation Error Determination and LoggingINTRQ# Interrupt Error Conditions WXB as Bus Master WXB as Target Other Violations Discard Timer Expiration PCI Interface ErrorsSystem Error Signaled AGP Subsystem Graphics Address Relocation Table Gart 22b 12b24b 14b Gart Implementation Gart Entry Format for 4kB Pages Gtlb Programming GartSizes Parity SE2 ADSC# ADSP# ADV# LBO# SB# SW# CoherencySGW# Interrupt Handling 4.1 3.3V AGP 1X and 2X Mode CompatibilityAGP Traffic Addresses Used by the Graphics Card Traffic Priority Coherency, Translation and Types of AGP Traffic Coherency for AGP/PCI Streams Ordering RulesProcessor Locks and AGP Traffic PCI Semantics Traffic Address FaultsAddress Alignment and Transfer Sizes Inbound Reads Inbound Reads Directed To Memory Inbound Delayed Read Matching RulesPCI Stream Read Prefetching Inbound I/O Reads Delayed Read Matching CriteriaCommand Address BEs Inbound Writes Outbound Writes Retry/Disconnect ConditionsOutbound Reads Burst Write Combining Modes Transfer Data Length Combining Supported Used ModeFast Back-to-Back Transactions 1st write 2nd write 3rd write Transferred as Inbound Read Prefetching LatencyGXB Address Map Bandwidth Estimates for Various Request Sizes AGP Subsystem AGP Subsystem Ihpc Configuration Registers WXB Hot-Plug Ihpc Configuration Register Space Did Device Identification Register Number List for the Ihpc PCI Register DescriptionsVID Vendor Identification Register Pcicmd PCI Command Register Pcists PCI Status Register RID Revision Identification Register CLS Cache Line Size MLT Master Latency Timer RegisterClass Class Register HDR Header Register SID Subsystem ID Base AddressSvid Subsystem Vendor Identification Interrupt Line Hot-Plug Slot Identifier Miscellaneous Hot-Plug ConfigurationInterrupt Pin Power Fault Serr Status Hot-Plug FeaturesSwitch Change Serr Status Ihpc Memory Mapped Registers Memory Access IndexMemory Mapped Register Access Port Arbiter Serr Status Ihpc Memor Mapped Register Space M66EN Slot Enable Number List for Ihpc Memory Mapped Register Descriptions Hot-Plug Miscellaneous LED Control Hot-Plug Interrupt Input and Clear Hot-Plug Interrupt Mask Serial Input Byte Data Hot-Plug Non-interrupt Inputs Serial Input Byte PointerGeneral Purpose Output Extended Hot-Plug Miscellaneous Hot-Plug Switch Interrupt Redirect EnableSlot Power Control Mnemonic Register Register Access PCI / LPC / FWH ConfigurationPCI Configuration Registers Function IFB Register Mapping Classc BiosenPcists Hedt IDE Configuration PCI Configuration Registers-Function 1 IDE Interface Configuration Offset Mnemonic Register Universal Serial Bus USB ConfigurationPCI Configuration Registers-Function 2 USB Interface SMBus Controller Configuration SMBus Configuration Registers Function IFB Register Mapping CD-ROM Auto RUN Feature of the OS Usage of 1MIN Timer in Power ManagementUsage of the SW SMI# Timer IFB Usage Considerations Disabled Enabled Ultra DMA ConfigurationReserved Secondary Primary Drive Ultra DMA Mode Enable SSDE1 SSDE0 PSDE1 PSDE0 Capability Word Bits Field Offset Determining a Drive’s Transfer Rate CapabilitiesOverview Ultra DMA Fields that Indicate Ultra DMA Drive Capabilities PIO Capability Word BitsDMA Determining a Drive’s Best Ultra DMA Capability Capability Word Bits Field 10-6 Capability Word Offset Bits Field150 Minimum Multi Word DMA Transfer Cycle Time per Drives Reported DMA Drive’s Best DMA Mode Cycle Time Determining a Drive’s Best PIO Capability Drives Reported PIO Drive’s Best PIO Mode Drive PIO Capability as a Function of Cycle Time IFB Drive Mode Based on DMA/PIO Capabilities IFB Timing Settings10.5.6.1 DMA/PIO Timing Settings Mode Yes Disabled Enabled DMA Mode Iordy If fixed disk DMA Iordy IDE 10. Ultra DMA Timing Value Based on Drive Mode Drive Configuration for Selected TimingsUltra DMA Timing Settings DMA/PIO Timing Values Based on Piix Cable Mode/System Speed 10-12 12. PIO Transfer/Mode ValuesDrive’s Selected PIO Speed Capability Settings Checklist 13. Drive Capabilities Checklist 14. IFB Settings Checklist Example ConfigurationsExample #1 Ultra DMA/33 Configuration Register Type Offset Value Comments 4A-4Bh 0002h Ultra DMA mode config Example #3 Non Ultra DMA/33 Drive Configuration40-41h E377h Mode config. for Primary IDE Timing Register 44h 0Bh Ultra DMA Control Register 10-16 Ultra DMA System Software Considerations4A-4Bh 0000h Intel 460GX Chipset Software Developer’s Manual 10-17 Bit Description Bit Description Reserved. This bit is hardwired toBMISX-Bus Master IDE Status Register I/O Completed or halted USB Resume Enable Bit Bit Type Description 10-20 DID-Device Identification Register Function LPC/FWH Interface ConfigurationVID-Vendor Identification Register Function PCICMD-PCI Command Register Function PCISTS-PCI Device Status Register Function HEDT-Header Type Register Function RID-Revision Identification Register FunctionCLASSC-Class Code Register Function Bit SCI IRQ Routing Control Acpi Enable FunctionAcpi Base Address Function BIOSEN-BIOS Enable Register Function PIRQRCAD-PIRQx Route Control Registers Function SerIRQC-Serial IRQ Control Register Function TOM-Top of Memory Register Function MSTAT-Miscellaneous Status Register Function Deterministic Latency Control Register Function Bits Description PDMACFG-PCI DMA Configuration Resister Function OMGPIOC-Muxed Gpio Control Function RTCCFG-Real Time Clock Configuration Register Function Base Offset Channel LPC COM Decode Ranges Function Gpio Enable FunctionGpio Base Address Function Bits Decode Range 011 LPC FDD/LPT Decode Ranges Function000 110 220 233 240 253 260 273 280 293 LPC Sound Decode Ranges FunctionLPC Generic Decode Range Function 11-12 Reserved. This bit must be a LPC Enables FunctionFirmware Hub FWH Decode Enable Register 1413 Reserved Firmware Hub FWH Select Register PCI to LPC I/O Space Registers Test Mode RegisterDcom-Dma Command Register I/O DMA Registers Dcm-Dma Channel Mode Register I/O Dr-Dma Request Register I/O Bit Description Reserved. Must be WSMB-Write Single Mask Bit I/ORWAMB-Read / Write All Mask Bits I/O Ds-Dma Status Register I/O DBADDR-DMA Base and Current Address Registers I/O DLPAGE-DMA Low Page Registers I/O When counting down a DMA transferDBCNT-Dma Base and Current Count Registers I/O DCBP-Dma Clear Byte Pointer Register I/O Dmc-Dma Master Clear Register I/O 11.2.2.1 Icw1-Initialization Command Word 1 Register I/OInterrupt Controller Registers Dclm-Dma Clear Mask Register I/O Bit Description Reserved. Must be programmed to all 0s 11.2.2.2 Icw2-Initialization Command Word 2 Register I/O11.2.2.3 Icw3-Initialization Command Word 3 Register I/O 11.2.2.6 Ocw1-Operational Control Word 1 Register I/O 11.2.2.4 Icw3-Initialization Command Word 3 Register I/O11.2.2.5 Icw4-Initialization Command Word 4 Register I/O 11-22 11.2.2.7 Ocw2-Operational Control Word 2 Register I/O 11.2.2.8 Ocw3-Operational Control Word 3 Register I/O Elcr1-Edge/Level Control Register I/O Elcr2-Edge/Level Control Register I/O Counter/Timer RegistersTcw-Timer Control Word Register I/O Bit Decription 5. When bit 2=0, status and/or count will not be latched Latched. When bit 4=1, the status will not be latched5. When bit 3=0, status and/or count will not be latched 5. When bit 1=0, status and/or count will not be latched TMRSTS-Timer Status Registers I/O TMRCNT-Timer Count Registers I/O NMI Registers Nmisc-Nmi Status and Control Register I/O RTCD-Real-time Clock Data Register I/O NMI Enable. Used by IFB NMI logicReal Time Clock Registers Used for NMI enabling/disabling. See description in Section RTCEI-Real-time Clock Extended Index Register I/O Advanced Power Management APM RegistersAPMC-Advanced Power Management Control Port I/O RTCED-Real-time Clock Extended Data Register I/O Acpi Registers APMS-Advanced Power Management Status Port I/OPower Management 1 Status States can be supported in external logic Power Management 1 EnablePower Management 1 Control 11-32 General Purpose 0 Status Power Management 1 TimerBit Description Bits Mode 3124 Reserved 230 1512 Reserved General Purpose 0 EnablePower up, this bit is set to ‘1’ CF9 write General Purpose 1 Status General Purpose 1 EnableSMI Registers Status Register is set Global Control and EnablePort at B2h in I/O space Thrmsts bit GPIO8 General Purpose I/O RegistersGlobal Status Register GPIO7 GP Output GP Data 159 Reserved GP TTL1916 Bit is set GP Invert GP BlinkGP Lock GP Core GP SMIGP Pulse GP Pull-up 11-42 Configuration Mnemonic Register IDE ConfigurationPCI Configuration Registers Function IDE Controller Register Descriptions PCI Function Parity Error Response. This bit is hardwired to SERR# Enable. This bit is hardwired toWait Cycle Control. This bit is hardwired to VGA Palette Snoop. This bit is hardwired to SERR# Status. Read as By writing a 1 to this bit Bus Master interface registers and correspond to AD154 MLT-Master Latency Timer Register FunctionBMIBA-Bus Master Interface Base Address Register Function IDETIM-IDE Timing Register Function SVID-Subsystem Vendor ID FunctionSID-Subsystem ID Function SIDETIM-Slave IDE Timing Register Function DMACTL-Synchronous DMA Control Register Function Bit Description Reserved SDMATIM-Synchronous DMA Timing Register Function IDE Controller I/O Space Registers BMICx-Bus Master IDE Command Register I/OUltra DMA/33 Timing Mode Settings Ultra DMA/33 Timing Modes BMISx-Bus Master IDE Status Register I/O 312 Interrupt/Activity Status CombinationsIs equal to the IDE device transfer size 12-12 Usbren Universal Serial Bus USB ConfigurationPCI Configuration Registers-Function Reserved. Read as USB Host Controller Register Descriptions PCI FunctionBit Description 1510 Reserved. Read Resets STA to 0 by writing a 1 to this bit Reserved. Read as 0’s 13-4 This fieldRegister in Function USBBA-USB I/O Space Base Address Function INTLN-Interrupt Line Register Function SBRNUM-Serial Bus Release Number Function INTPN-Interrupt Pin FunctionMiscellaneous Control Function LEGSUP-Legacy Support Register Function Appropriate enable bits are set Default to 1 for compatibility with older USB softwareNeeds to be serviced later Accesses that are part of the sequence USB Host Controller I/O Space Registers USBREN-USB Resume EnableUSBCMD-USB Command Register I/O Stop=0, the Frnum register can be reprogrammed Run/Stop, Debug Bit InteractionSwdbg Bit Run/Stop Bit Operation By Software or Hardware Interrupt is generated to the system USBINTR-USB Interrupt Enable Register I/OUSBSTS-USB Status Register I/O Register = FLBASEADD-Frame List Base Address Register I/O Address signalsFRNUM-Frame Number Register I/O SOFMOD-Start of Frame SOF Modify Register I/O PORTSC-Port Status and Control Register I/O EOF2 time See of the USB Specification X0 DisableAsserted, the corresponding port is disabled Register define the hub states as follows 13-14 Class Code 0C-1Fh Reserved SM Bus Controller ConfigurationSM Bus Configuration Registers Function Base Address Register 14-2 System Management Register DescriptionsShutdown special cycle STA to 0 by writing a 1 to this bit SMBBA-SMBus Base Address Function 14-4 Host Configuration Interrupt pin PIRQB# is used Smbshdw1-SMBus Slave Shadow Port 1 Function Smbslvc-SMBus Slave Command FunctionSMBus I/O Space Registers Smbshdw2-SMBus Slave Shadow Port 2 Function Smbslvsts-SMBus Slave Status Register I/O Transaction errors are caused bySmbhststs-SMBus Host Status Register I/O Position Smbhstcnt-SMBus Host Control Register I/O Smbhstadd-SMBus Host Address Register I/O Smbhstcmd-SMBus Host Command Register I/OCommand field of SMBus host transaction Smbhstdat0-SMBus Host Data 0 Register I/O Smbslvcnt-SMBus Slave Control Register I/O Smbhstdat1-SMBus Host Data 1 Register I/OSmbblkdat-SMBus Block Data Register I/O 14.3.9.2 10.3.11.smbslvevt-SMBus Slave Event Register I/O 14.3.9.1 Smbshdwcmd -SMBus Shadow Command Register I/OSmbslvdat-SMBus Slave Data Register I/O Address 10h or one of the slave shadow port addresses 14-12 Interrupt Controller PCI/LPC Bridge DescriptionPCI Interface 15-2 Initialization Command Words ICWsProgramming the Interrupt Controller End of Interrupt Operation Operation Command Words OCWsAutomatic End of Interrupt Aeoi Mode End of Interrupt EOI Modes of Operation Fully Nested ModeSpecial Fully Nested Mode Automatic Rotation Equal Priority Devices Specific Rotation Specific Priority Cascade ModePoll Command Interrupt Masks Edge and Level Triggered ModeSpecial Mask Mode Masking on an Individual Interrupt Request Basis Reading the Interrupt Controller Status Interrupt Steering Serial Interrupts Quiet Active ModeContinuous Idle Mode Protocol Data Frame Number Usage # Clocks Past Start Stop FrameSerirq Frames 3222 15-10 Timer/CountersProgramming the Interval Timer Interval Timer Control Word Format Write Operations Counter I/O Port Read Counter Latch CommandRead Operations 15-12 Read Back Command Real Time Clock Index Address Name RTC Registers and RAMRTC Standard RAM Bank 90625 ms 8125 ms 15.5.1.1 Register a1 Invalid 0 Invalid RSMRST# 15.5.1.2 Register B15.5.1.3 Register C Lockable RAM Ranges RTC Update CycleRTC Interrupts 15.5.1.4 Register D 15-18 Overview IFB Power ManagementIFB Power States and Consumption Acpi State Description 16.2.2 SMI# Generation IFB Power PlanesPower Plane Descriptions Causes of SMI# Causes of SCI# SCI GenerationSleep States SCI Event Comment Acpi Bits Not Implemented in IFB Acpi Bits Not Implemented by IFBEntry/Exit for the S4 and S5 States Offset Register Name/Function Comment S5 Wake Event Comment Handling of Power Failures in IFBAction after Power Returns 16-6