Data Integrity and Error Handling

Table 6-1. Error Cases (Cont’d)

Error

Chip

System

Status

 

Log

Qualifier

Detecting

Action

Register

 

Register

 

 

 

 

 

 

 

 

 

 

GART Parity Error

GXB

Continue, use address

FERR_GART

Nothing

 

GARTER

 

 

as read from GART,

 

 

 

R_BINITE

 

 

Unconditional XINTR#,

 

 

 

 

 

 

Conditional XBINIT#.

 

 

 

 

 

 

(NOTE: if XBINIT# is

 

 

 

 

 

 

driven, then it is not

 

 

 

 

 

 

required to drive

 

 

 

 

 

 

XINTR#)

 

 

 

 

 

 

 

 

 

 

 

Illegal SMM

GXB

Unconditional XBINIT#

FERR_GART

Nothing

 

 

Access

 

 

 

 

 

 

 

 

 

 

 

 

 

Illegal Address

GXB

Unconditional XBINIT#

FERR_GART

Nothing

 

 

 

 

 

 

 

 

 

Illegal OB GART

GXB

Unconditional XINTR#,

FERR_PCI

Nothing

 

GARTER

Access

 

Conditional XBINIT#,

 

 

 

R_BINITE

 

 

results undefined.

 

 

 

 

 

 

 

 

 

 

 

PXB Errors

 

 

 

 

 

 

 

 

 

 

 

 

 

Detected at

 

 

 

 

 

 

Expander Port

 

 

 

 

 

 

 

 

 

 

 

 

 

Expander Par-err

PXB

Set Status. If outbound

PCISTS [SSE],

Nothing

 

MODES

on any Header

 

error handling is enabled

ERRSTS[2]

 

 

[3]

 

 

then assert BINIT#, else

 

 

 

 

 

 

then SERR#, drop

 

 

 

 

 

 

request (no cmplt

 

 

 

 

 

 

returned).

 

 

 

 

 

 

 

 

 

 

 

Expander Par-err

PXB

Set Status. If outbound

PCISTS [SSE],

Nothing

 

MODES

on Write Data from

 

error handling in enabled

ERRSTS[2]

 

 

[3]

Expander

 

then poison data as

 

 

 

 

 

 

passed to PCI, else then

 

 

 

 

 

 

SERR# and write out

 

 

 

 

 

 

data as good to PCI.

 

 

 

 

 

 

 

 

 

 

 

Expander HF Read

PXB

PXB: Set Status. Target

PCISTS [STA]

Nothing

 

 

Cmplt. from SAC

 

abort read to card.

 

 

 

 

 

 

(Received in peer-to-

 

 

 

 

 

 

peer)

 

 

 

 

 

 

 

 

 

 

 

Expander Par-err

PXB

Set Status. If outbound

ERRSTS[2],

Nothing

 

MODES

on IB Read Data

 

error handling is enabled

PCISTS[SSE]

 

 

[3]

 

 

then poison data as

 

 

 

 

 

 

passed to PCI, else then

 

 

 

 

 

 

SERR# and pass read

 

 

 

 

 

 

data as good to PCI.

 

 

 

 

 

 

 

 

 

 

 

Detected as PCI Master

 

 

 

 

 

 

 

 

 

 

 

 

PCI Par-err on OB

PXB

Set Status. Drive

ERRSTS[5], PCISTS[PE],

Nothing

 

 

Read Data

 

PERR#. Pass data with

PCISTS[DPE]

 

 

 

Received from

 

good parity to Expander.

 

 

 

 

Card

 

(PERR# is optionally

 

 

 

 

 

 

elevated to SERR#)

 

 

 

 

 

 

 

 

 

 

 

Master Abort on

PXB

Return all 1’s

PCISTS [RMA]

Nothing

 

 

Read Done by PXB

 

 

 

 

 

 

 

 

 

 

 

 

 

Master Abort on

PXB

Drop data, normal CMP

PCISTS [RMA]

Nothing

 

 

Write Done by PXB

 

 

 

 

 

 

 

 

 

 

 

 

 

Target Abort

PXB

Return HF to either read

PCISTS [RTA]

Nothing

 

 

received by xXB

 

or write. If failed access

 

 

 

 

 

 

is in middle of

 

 

 

 

 

 

transaction then the

 

 

 

 

 

 

remainder of the

 

 

 

 

 

 

transaction is discarded.

 

 

 

 

 

 

 

 

 

 

 

PERR# Asserted

card

Optionally turned to

ERRSTS[6],

Nothing

 

 

by Card

 

SERR# by PXB.

PCISTS[DPE]

 

 

 

 

 

 

 

 

 

 

Intel® 460GX Chipset Software Developer’s Manual

6-19