Intel 460GX manual SCI Generation, Sleep States, Causes of SCI#, SCI Event Comment

IFB Power Management

16.2.3SCI Generation

In an ACPI environment, an SCI (system control interrupt) must be generated for any event that must be handled by ACPI software. If the SCI_EN bit is set, the IFB will generate an SCI based on the sources listed below in Table 16-3. Each source can be individually enabled/disabled.

Table 16-3. Causes of SCI#

SCI Event	Comment
Overflow of ACPI Timer	Time-out every 2.34 seconds. If SCI_EN is not set, the timer
	overflow will instead cause an SMI#.
THRM# Signal	The THRM# can cause an SCI# on either the rising or falling
	edge. If the SCI_EN is not set, the THRM# signal will instead
	cause an SMI#.
Setting of the BIOS_RLS Bit	This bit is set by the firmware to cause an SCI. The ACPI
	handler will clear the bit.
GPIO Assertion	When a GPIO bit is programmed as an input, and the register bit
	is set to a ‘1’. The bit will be cleared when the ACPI handler
	clears the asserting device.

SCI is a level mode interrupt. In non-APIC systems (default), the SCI IRQ is routed to IRQ9. The 8259 interrupt controller must be programmed to level mode for that interrupt. In APIC systems, the SCI IRQ can still be IRQ9, or can be routed to one of the APIC interrupts 20-23. In either case, the interrupt generated internally is active high level. The interrupt will remain high until all SCI sources are removed.

16.2.4Sleep States

The IFB directly supports several sleep states (two of which will typically be mapped to the ACPI S1 state). From a IFB perspective, the two S1 states only differ on whether the SLP# signal is active. Additional Sleep states, such as S4 and S5 are also supported.

The entry to the Sleep states are based on several assumptions:

•After setting the SLP_EN bit, the IFB will assert the STPCLK# pin. The IFB will not continue to step through the sleep sequence unless the Stop Grant special cycle is received on the PCI bus.

•Entering the Sleep state without at least one wake event set is not recommended. This could lock up the system. However, the power button will always be a wake event.

•If using the S1 Sleep state with SLP# active, the PCI masters must be prevented from accessing memory, because the CPU cannot maintain cache coherence.

•In either of the IFB S1 Sleep states, the PCI clock will still be running, so the Serial IRQ stream will still be available. DMA, USB, and IDE will not be available, because the IFB bus masters will not be able to access main memory. The USB controllers, can still generate WAK event, however.

•In the S4 or S5 Sleep states, the PCI clock will NOT be running (and the PCI bus unpowered), so the Serial IRQ stream will NOT be available. If an external device is still powered during S4-S5, it should use some other mechanism to request that the IFB wakes the system.

•Upon exit from any Sleep states, the WAK_STS bit will be set.

•Upon exit from any Sleep state, the SLP_TYP bits will contain the originally programmed values.

Intel® 460GX Chipset Software Developer’s Manual 16-3