Intel 460GX 2.5.4GXB, Overflow, 39Overflow, Bits Description, 5:0 Event Selection, Bus Signal Assertions, Individual Bus Transactions, Generic (Grouped) Bus Transactions

Register Descriptions

5:0 Event Selection

This field specifies the basic PCI bus transaction or PCI bus signal to be monitored.

Individual Bus Transactions
00 0000	reserved	00 1000	reserved
00 0001	reserved	00 1001	reserved
00 0010	I/O Read	00 1010	reserved
00 0011	I/O Write	00 1011	reserved
00 0100	reserved	00 1100	Memory Read Multiple
00 0101	reserved	00 1101	Dual Address Cycle
00 0110	Memory Read	00 1110	Memory Read Line
00 0111	Memory Write	00 1111	Memory Write & Invalidate
Generic (Grouped) Bus Transactions
010 000	Any bus transaction	010 100	Any I/O transaction
010 001	Any memory transaction	010 101	Any I/O or memory
			transactions
010 010	Any memory read	010 110	Any I/O or memory read
010 011	Any memory write	010 111	Any I/O or memory write
Bus Signal Assertions
011 000	reserved	011 100	reserved
011 001	reserved	011 101	reserved
011 010	RETRY1	011 110	LOCK
011 011	reserved	011 111	ACK64

All other encodings are reserved.

NOTE:1. Counting data cycles is undefined for this selection.

2.5.4GXB2.5.4.1AGP_PMD_0,1: AGP Performance Monitor Data Registers

Function Number:	BFN+1
Address Offset:	50h, 58h	Size:	64 bits
Default Value:	0	Attribute:	Read/Write
Sticky:	No	Locked:	No

This counter may be configured to track AGP bus events as well as events internal to the GXB. Event detection may be configured to increment a counter, affect performance monitoring pins, and issue an interrupt request on counter overflow.

The value written to this address, loads the counter and is also saved in a reload register. Each counter can be configured to reload the data.

The AGP_G_PMD register holds the performance monitoring count value. 39-bits of the counter are used for event counting, the 40th-bit is used as a overflow detection bit. The 39-bit count value allows up to 70 minutes of event collection at 133 MHz. Event selection is controlled by the PMC registers.

Each counter may be stopped/started independently, using the controls available in the associated PMD register.

Bits Description

63:40 reserved(0)

39Overflow

This bit is asserted when the Event Count bit 38 carries into bit 39.

2-38 Intel® 460GX Chipset Software Developer’s Manual