Data Integrity and Error Handling

•DEDF - first double-bit ECC error on the system bus.

•PCMD - first parity error on the command bus.

•PITID - first parity error on the ITID bus.

•SDCRSP - first failing transmission on the response bus. The response bus does not have parity, instead it sends the response in clock x and the inversion of the response in clock x+1.

All of these registers are independent. Having one of these valid doe not block any other from being valid. They record the first error of each type. Each one is locked only when the bit which is associated with the particular error in either SDC_FERR or SDC_NERR is set. In theory all the above registers could contain valid error information. There may be many cases where there are both single and double bit errors set as valid, especially if the single-bit errors are not scrubbed. If one whole line is bad both FERR and NERR get set, since each data chunk of 16B is considered as an independent unit.

Note: The error logging registers are enabled anytime the FERR and NERR registers both have the appropriate bit cleared. If an error is found and the FERR and NERR registers are cleared, then the next error will overwrite the old value in the logging register. If FERR or NERR is not cleared, then new errors will not overwrite the logging register.

6.7Clearing Errors

Firmware or the operating system must clear out all the error registers when returning from a BINIT# or a reset. Leaving error bits set in the error registers will cause the system to flag that an error from an earlier time is still present. Firmware should read each FERR and NERR register and log any bits that are set. It should then clear those bits and continue to the next group of error registers.

6.7.1SAC/SDC Error Clearing

In the case of a data error, both the SAC and SDC will log the event. After handling the error, software should clear the error logging in the following order

•Read the SECTID, DEDTID, or FSETID register as above

•Clear the SECTID, DEDTID or FSETID registers by writing a ‘1’ to bit 6 of the appropriate register

•Clear the SAC_NERR register if set

•Clear the SAC_FERR register

•Clear the SDC error registers only after the SAC’s registers are cleared

•Re-read the error registers to make sure they are still clear

•Re-enable interrupts or other system signaling

6.8Multiple Errors

With the number of errors that are detected in the 460GX chipset, there are many possible multiple error cases. There is no way to specify what can happen in the case of every combination. In general the first error that is found is the important one. If there is only one error then it may be possible for the operating system to recover and continue without a full re-boot of the system. If there is more than one error, except for correctable ECC errors, then the system is probably not

Intel® 460GX Chipset Software Developer’s Manual

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