Data Integrity and Error Handling

6.1.2DRAM

•The 460GX chipset provides ECC generation on all writes into the DRAM, and ECC checking on all reads from the DRAM. Single-bit errors are corrected. Multi-bit errors will return poisoned data. Both types of errors are logged, with the address and ECC bits for the data being recorded. The row which failed, as well as the bit for single-bit errors, can be identified by software.

•The first instance of a single-bit error is logged. After the first error, additional status flags indicate subsequent errors occurred. The first multi-bit error is logged, with a status bit indicating there were more uncorrectable errors. In both cases, software can clear the error register and reset the error capture logic.

•Single-bit errors are corrected as they are received.

•To facilitate component debug and diagnostics, the ECC code generated on writes into the DRAM can be forced incorrect. A configuration bit, when set, will force the ECC bits that are written into memory to be XOR’ed with the correct value. This will allow either single or double bit failures to be generated in memory. When the data is read, the system should correct the data and report the error for single-bit errors, or report the error for double bit errors while passing bad ECC to the processor.

6.1.3Expander Buses

•Parity bits are generated and checked independently for each Expander bus. For error behavior see Table 6-1.

•Hard Fail responses are supported.

•A mechanism for elevating fatal errors to BINIT# (XBINIT#) and non-fatal errors to BERR# (XBERR#) is provided.

6.1.4PCI Buses

•Parity bits are generated and checked independently for each PCI bus.

•Standard PCI checking for aborts, PERR# and SERR# are also done.

6.1.5AGP

•There is no parity on the bus between the graphics card and the GXB when using AGP protocol. Transactions using PCI protocol have parity as defined for the standard PCI bus.

•The GXB checks for illegal or unknown operations, Expander bus parity errors, or internal parity errors.

•There is parity on the GART table.

6.1.6Private Bus between SAC and SDC

•There will be parity on the 64 bit data bus. Errors on data into the SDC will poison the data in the DB. Errors on data into the SAC will always be passed on without correction, with an option to BINIT#.

•The command bus and ITID bus are parity protected. Parity errors on this bus cause a BINIT#.

6-2

Intel® 460GX Chipset Software Developer’s Manual