Data Integrity and Error Handling

The default option is to return a “normal” response. If the aborted transaction was a read, the PXB will return all 1’s for the data. If the aborted transaction was a write, the PXB will discard the write data. SERR# is not asserted in either case.

6.11.2.2Received Target Disconnect

A PCI target may issue a disconnect to indicate it is unable to respond within the PCI latency guidelines. Disconnect is signalled when the target asserts both STOP# and DEVSEL#. The target controls whether another data transfer may occur by whether TRDY# is asserted when STOP# is asserted. A target disconnect is not usually issued on the first data phase of the transaction. Target disconnects are not considered errors, and are not logged or reported in any way. After a target disconnect, the PXB will wait at least two PCI clocks before re-arbitrating for the PCI bus to complete the transfer.

6.11.2.3Received Target Retry

A PCI target may issue a retry to indicate that it is currently unable to process the transaction. Retry is signalled when the target asserts STOP# and DEVSEL# and does not assert TRDY#. Retry is actually a special case of disconnect that occurs before the first data transfer.

After receiving a retry for a transaction, the PXB will wait at least two PCI clocks before re- arbitrating for the PCI bus to retry the transaction. If the transaction is a write, the PXB will retry the transaction until it succeeds. If the transaction is a read, the PXB will retry the transaction until it succeeds, but may allow writes to pass it. Note, in all of these cases the retries are not considered errors. There is no logging or error reporting of any kind.

6.11.2.4Received Target Abort

A PCI target may issue an abort to indicate that the current transaction should be terminated and should not be attempted again. This is a catastrophic failure. Target abort is signalled when STOP# is asserted and DEVSEL# is deasserted. The PXB will log the target abort by setting the PCISTS register’s Received Target Abort (RTA) bit. The PXB then returns a hard fail response to the SAC.

6.11.2.5Data Parity Errors

When the PXB is the PCI bus master, it will check the data parity provided during read data cycles, and watch for the assertion of PERR# during write data cycles. See the earlier tables for exact details.

6.11.2.6Other Violations

The PCI specification identifies numerous cases that are violations of the PCI protocol. Other than the cases identified above, the PXB makes no attempt to check for such violations. Response to such violations is undefined. Refer to the PCI specification for a complete description of the required PCI protocol.

6.11.3PXB as Target6.11.3.1Target Disconnect

The PXB will issue a target disconnect under the following circumstances:

Intel® 460GX Chipset Software Developer’s Manual

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