2 SDC, 2.1 SEC0DFERR Data on First Memory Card B SEC | Intel 460GX

Register Descriptions

2.4.2SDC

2.4.2.1SEC0_D_FERR: Data on First Memory Card B SEC

Bus CBN, Device Number:	04h
Address Offset:	40-47h	Size:	64 bits
Default Value:	0	Attribute:	Read Only, New Value Latched
			anytime appropriate FERR register
			bit is set

This register records and latches the data corresponding to the first SEC detected by memory interface 0 in the SDC.

Bits Description

63:0 DE - System Data of Error.

2.4.2.2SEC0_ECC_FERR: ECC on First Memory Card B SEC

Bus CBN, Device Number:	04h
Address Offset:	48h	Size:	8 bits
Default Value:	00h	Attribute:	Read Only, New Value Latched
			anytime appropriate FERR register
			bit is set

This register records and latches the ECC checkbits corresponding to the first SEC detected by memory interface 0 in the SDC

Bits Description

7:0 ECC - ECC of Error.

2.4.2.3SEC0_TXINFO_FERR: TXINFO on First Memory Card B SEC

Bus CBN, Device Number:	04h
Address Offset:	49-4Ah	Size:	16 bits
Default Value:	00h	Attribute:	Read Only, New Value Latched
			anytime appropriate FERR register
			bit is set

This register records the ITID and failing chunk corresponding to the first SEC detected by memory interface 0 in the SDC.

Bits Description

15:9 reserved(0)

8:6 DC - Data Chunk of ITID.

5:0 ITID - ITID of error.

Intel® 460GX Chipset Software Developer’s Manual

2-11

Image 31

Intel 460GX manual 2 SDC, 2.1 SEC0DFERR Data on First Memory Card B SEC, 2.2 SEC0ECCFERR ECC on First Memory Card B SEC

Contents

Intel 460GX Chipset System Software Developer’s Manual Intel 460GX Chipset System Software Developer’s Manual Contents Coherency 10.1 Latency 10-1 11-8 13.2.4 Figures Tables 12-11 System Overview Introduction Intel 460GX Chipset Components Component OverviewName Function Itanium Processor System Bus Support Product Features Dram Interface Support PXB FeaturesI/O Support GXB Features RAS Features Programmable Interrupt Device PID Other Platform ComponentsReference Documents 1 I/O & Firmware Bridge IFB Date Description June Initial release Revision History Introduction Register Descriptions Access Mechanism Device Access RestrictionsPartitioning Device Mapping on Bus CBN Reserved or Undefined Register Locations Default Upon ResetRegister Attributes Reserved Bits Defined in Registers Gart Programming Region Configaddress Configuration Address RegisterI/O Mapped Registers Consistency 1.1 Error Handling RegistersConfigdata Configuration Data Register 1 SAC Valid Bits Description Disable1.2 1.3 Ferrsac First Error Status Register Nerrsac All Error Status Register Biuitid BIU Itid Register Saferr System Address on First Error Address bits Biudata BIU Data Register 2.3 SEC0TXINFOFERR Txinfo on First Memory Card B SEC 2 SDC2.1 SEC0DFERR Data on First Memory Card B SEC 2.2 SEC0ECCFERR ECC on First Memory Card B SEC 2.7 SEC1DFERR Data on First Memory Card a SEC 2.4 DED0DFERR Data on First Memory Card B DED2.5 DED0ECCFERR ECC on First Memory Card B DED 2.6 DED0TXINFOFERR Txinfo on First Memory Card B DED 2.9 SEC1TXINFOFERR Txinfo on First Memory Card a SEC 2.8 SEC1ECCFERR ECC on First Memory Card a SEC2.10 DED1DFERR Data on First Memory Card a DED 2.11 DED1ECCFERR ECC on First Memory Card a DED Sdcferr First Error Status Register2.12 DED1TXINFOFERR Txinfo on First Memory Card a DED 14 ’Forward’ Underflow Card B Left Stack Error FL0 22 ’Forward’ Underflow Card a Right Stack Error FR121 ’Forward’ Underflow Card a Left Stack Error FL1 15 ’Forward’ Underflow Card B Right Stack Error FR0 Pcmdferr Command on First Pcmd Parity Error Sdcnerr SDC Next Error Status RegisterPitidferr Data on First Pitid Parity Error Dpbrleferr Private Data Bus Receive Length Error Sdcrspferr Response on First Sdcrsp ErrorECCMSK0 ECC Mask Register Card B ECCMSK1 ECC Mask Register Card a ParMskP PB Parity Mask and IB Correction Enable RegisterEccmskf ECC Mask Register Pvdparferr Parity on First PVD Parity Error Pvddferr Data on First PVD Parity ErrorPvdtxinfoferr Txinfo on First PVD Parity Error Dedfdferr Data on First System Bus DED Secfdferr Data on First System Bus SECSecfeccferr ECC on First System Bus SEC Secftxinfoferr Txinfo on First System Bus SEC Dedfeccferr ECC on First System Bus DED Ferrmac First Error Status RegisterQue-Overflow Error 3 MAC Errsts Error Status Register Cmndferr Command on First Error4 PXB Errcmd Error Command Register Ferrpci Ferragp First Error Status Register for AGP5 GXB 5.1 Nerragp Next Errors Status Register for AGP Ferrgart First Error Status Register for Gart Pderr PCI Data First Error Pacerr PCI Address & Cmd First ErrorNerrgart Bits Description Intrq Asserted Flag Nepci Register Records an PCI Bus Error FlagFepci Register Records an PCI Bus Error Flag 6 WXB Fepci PCI Bus First Error Status Register Nepci PCI Bus Next Error Status Register 6764 C/BE30 6332 AD6332 310 AD310 Fepcial PCI First Error Address/Command LogFepcidl PCI First Error Data Log Performance Monitor Registers Dmask Encodings OverflowCount Value Length Encodings Event Select Umask Encodings Enable Source Disable SourceReload Control 2 SDC FSBDPMD1,0 System Bus Performance Monitor Data Registers 3.1 PMD10 Performance Monitoring Data Register 3 PXB3.2 PMR10 Performance Monitoring Response Initiating Agent Selection Reload Mode3.3 PME10 Performance Monitoring Event Selection Count Data Cycles AGPPMD0,1 AGP Performance Monitor Data Registers 4 GXB Percon Performance Monitor Control Register Pcipmd PCI Performance Monitor Data RegistersEvent 1 Input Event 0 Input AGPPMC0,1 AGP Performance Monitor Configuration RegisterPipe or Sideband Request Mask EVENT1 Count Enable Pcipmc PCI Performance Monitor Configuration RegisterInitiating Agent Disable Source Issuing Agent Qualifier PCIWXBPMC0 PCI Performance Monitor Configuration Register5 WXB Data Transfer and Transaction Qualifier Interrupt Related Registers PCIWXBPMC1 PCI Performance Monitor Configuration RegisterXtprs External Task Priority Registers Memory-Mapped Register Summary Address Name Access Default ValuePID PCI Memory-mapped Registers 2.1 I/O Register Select Register FEC00000h I/O Window Register Format PID Indirect Access Registers2.2 I/O Window Register FEC00010h XAPIC EOI Register FEC00040h 3.1 I/O xAPIC ID Register 00h Offset Name Access Default ValueRTE Memory-mapped Register Summary Cont’d I/O xAPIC Version Register Format 3.2 I/O xAPIC Version Register 01h3.3 I/O xAPIC Arbitration ID Register 02h I/O Apic ID Register Format 10. I/O xAPIC RTE Format Bits Sapic Mode Apic Mode Description Name3.4 I/O xAPIC RTE 10h-8Fh I/O xAPIC Arbitration ID Register Format 10. I/O xAPIC RTE Format Cont’d Sapic Mode Apic Mode Description Name Vector Destination Coherency System ArchitectureProcessor Coherency PCI Coherency OrderingAGP Coherency WXB Arbitration at the PCI Bus WXB ArbitrationArbitration for Inbound Transactions Arbitration for Outbound Transactions Big-endian SupportIndivisible Operations Processor Locks Locks with AGP Non-coherent Traffic Inbound PCI LocksAtomic Writes Atomic Reads WXB PCI Hot-Plug Support Interrupt Delivery Slot Power-down and Disable Slot Power-up and Enable System Architecture Memory Map System Address MapCompatibility Region System Memory Address Space System Firmware Medium Extended Memory Region Low Extended Memory Region Re-mapped Memory Areas High Extended Memory above 4GVariable GAP Itanium Processor and Chipset-specific Memory Space I/O Address Map System I/O Address Space High PXB must ignore GXB must BINIT# after Gart Devices View of the System Memory Map Address Disposition Legal and Illegal Address DispositionAddress Range Outbound Inbound Dest. Decision Binit Address Disposition Cont’dMain memory if present above 4 GB Above TOM System Address Map System General Memory CharacteristicsMemory Subsystem Organization Maximum Memory Configuration Using Two Cards Double Number Memory Size Minimum/Maximum Memory Size per ConfigurationTechnology & Configuration Size Dimm Types Address Interleaving Interleaving/Configurations Non-uniform Memory Configurations Summary of Configuration RulesBandwidth Removing a Bad Row Supporting FeaturesMemory Subsystem Clocking Auto Detection Memory Size Time to Scrub Hardware InitializationMemory Scrubbing Scrubbing Time Memory Subsystem Integrity Data Integrity and Error HandlingSystem Bus 5 AGP DramExpander Buses PCI Buses Memory ECC Routing Usage of First-error and Next-errorData Poisoning BERR#/BINIT# Generation Masked BitsINTREQ# XSERR# SAC/SDC ErrorsData ECC or Parity Errors XBINIT# SAC to SDC Interface Errors System Bus Errors 5 SDC/Memory Card Interface Errors SAC to MAC Interface Errors 6 SDC/System Bus Errors Error DeterminationSDC Internal Errors SAC Address on an Error Special Notes on Usage of SECTID, DEDTID, Fsetid Registers SDC Logging Registers Multiple Errors Clearing Errors1 SAC/SDC Error Clearing ERR ERR SDC Multiple Errors Single Errors with Multiple Reporting SAC Multiple ErrorsError Anomalies SAC Error Flow on Data Data Flow Errors Table of Errors Error Conditions SAC to SDC Interface Errors Error CasesSystem Bus ADD/CMND Error Cases Cont’d Internal SDC Error Detected as PCI Master PXB Errors Master Abort PCI IntegrityPCI Bus Monitoring PXB as Master PXB as Target Target Retry GXB Error FlowTarget Abort GXB Errors GXB Error Signals Gart Interface Errors GXB Error Flow Multiple Errors Data Parity Poisoning WXB Data Integrity and Error HandlingUsage of First Error and Next Error Registers Integrity Abbreviation Error Error Mask BitsError Steering/Signaling Supported Error Escalation to XBINIT#a Escalation Supported Error Escalation to SERROUT#aSupported Error Escalation to PA/BINTRQ# SERR# Generation INTRQ# Interrupt Error Determination and LoggingXBINIT# Generation WXB as Bus Master Error Conditions Other Violations WXB as Target System Error Signaled PCI Interface ErrorsDiscard Timer Expiration Graphics Address Relocation Table Gart AGP Subsystem 14b 12b24b 22b Gart Entry Format for 4kB Pages Gart Implementation Parity Programming GartSizes Gtlb SGW# CoherencySE2 ADSC# ADSP# ADV# LBO# SB# SW# Addresses Used by the Graphics Card 4.1 3.3V AGP 1X and 2X Mode CompatibilityAGP Traffic Interrupt Handling Coherency, Translation and Types of AGP Traffic Traffic Priority Processor Locks and AGP Traffic Ordering RulesCoherency for AGP/PCI Streams Inbound Reads Address FaultsAddress Alignment and Transfer Sizes PCI Semantics Traffic PCI Stream Read Prefetching Inbound Delayed Read Matching RulesInbound Reads Directed To Memory Inbound Writes Delayed Read Matching CriteriaCommand Address BEs Inbound I/O Reads Outbound Reads Retry/Disconnect ConditionsOutbound Writes 1st write 2nd write 3rd write Transferred as Transfer Data Length Combining Supported Used ModeFast Back-to-Back Transactions Burst Write Combining Modes Bandwidth Estimates for Various Request Sizes LatencyGXB Address Map Inbound Read Prefetching AGP Subsystem AGP Subsystem WXB Hot-Plug Ihpc Configuration Registers Ihpc Configuration Register Space VID Vendor Identification Register Number List for the Ihpc PCI Register DescriptionsDid Device Identification Register Pcicmd PCI Command Register RID Revision Identification Register Pcists PCI Status Register HDR Header Register MLT Master Latency Timer RegisterClass Class Register CLS Cache Line Size Interrupt Line Base AddressSvid Subsystem Vendor Identification SID Subsystem ID Interrupt Pin Miscellaneous Hot-Plug ConfigurationHot-Plug Slot Identifier Switch Change Serr Status Hot-Plug FeaturesPower Fault Serr Status Arbiter Serr Status Memory Access IndexMemory Mapped Register Access Port Ihpc Memory Mapped Registers M66EN Ihpc Memor Mapped Register Space Number List for Ihpc Memory Mapped Register Descriptions Slot Enable LED Control Hot-Plug Miscellaneous Hot-Plug Interrupt Input and Clear Hot-Plug Interrupt Mask Serial Input Byte Data General Purpose Output Serial Input Byte PointerHot-Plug Non-interrupt Inputs Slot Power Control Hot-Plug Switch Interrupt Redirect EnableExtended Hot-Plug Miscellaneous IFB Register Mapping PCI / LPC / FWH ConfigurationPCI Configuration Registers Function Mnemonic Register Register Access Hedt BiosenPcists Classc PCI Configuration Registers-Function 1 IDE Interface IDE Configuration PCI Configuration Registers-Function 2 USB Interface Universal Serial Bus USB ConfigurationConfiguration Offset Mnemonic Register SMBus Configuration Registers Function SMBus Controller Configuration IFB Register Mapping IFB Usage Considerations Usage of 1MIN Timer in Power ManagementUsage of the SW SMI# Timer CD-ROM Auto RUN Feature of the OS SSDE1 SSDE0 PSDE1 PSDE0 Ultra DMA ConfigurationReserved Secondary Primary Drive Ultra DMA Mode Enable Disabled Enabled Ultra DMA Fields that Indicate Ultra DMA Drive Capabilities Determining a Drive’s Transfer Rate CapabilitiesOverview Capability Word Bits Field Offset DMA Capability Word BitsPIO Capability Word Bits Field Determining a Drive’s Best Ultra DMA Capability 150 Minimum Multi Word DMA Transfer Cycle Time per Capability Word Offset Bits Field10-6 Determining a Drive’s Best PIO Capability Drives Reported DMA Drive’s Best DMA Mode Cycle Time Drive PIO Capability as a Function of Cycle Time Drives Reported PIO Drive’s Best PIO Mode Mode Yes Disabled Enabled DMA Mode Iordy If fixed disk IFB Timing Settings10.5.6.1 DMA/PIO Timing Settings IFB Drive Mode Based on DMA/PIO Capabilities DMA Iordy IDE DMA/PIO Timing Values Based on Piix Cable Mode/System Speed Drive Configuration for Selected TimingsUltra DMA Timing Settings 10. Ultra DMA Timing Value Based on Drive Mode Drive’s Selected PIO Speed Capability 12. PIO Transfer/Mode Values10-12 13. Drive Capabilities Checklist Settings Checklist Register Type Offset Value Comments Example ConfigurationsExample #1 Ultra DMA/33 Configuration 14. IFB Settings Checklist 44h 0Bh Ultra DMA Control Register Example #3 Non Ultra DMA/33 Drive Configuration40-41h E377h Mode config. for Primary IDE Timing Register 4A-4Bh 0002h Ultra DMA mode config 4A-4Bh 0000h Ultra DMA System Software Considerations10-16 Intel 460GX Chipset Software Developer’s Manual 10-17 Completed or halted Bit Description Reserved. This bit is hardwired toBMISX-Bus Master IDE Status Register I/O Bit Description Bit Type Description USB Resume Enable Bit 10-20 VID-Vendor Identification Register Function LPC/FWH Interface ConfigurationDID-Device Identification Register Function PCISTS-PCI Device Status Register Function PCICMD-PCI Command Register Function Bit RID-Revision Identification Register FunctionCLASSC-Class Code Register Function HEDT-Header Type Register Function Acpi Base Address Function Acpi Enable FunctionSCI IRQ Routing Control PIRQRCAD-PIRQx Route Control Registers Function BIOSEN-BIOS Enable Register Function TOM-Top of Memory Register Function SerIRQC-Serial IRQ Control Register Function Deterministic Latency Control Register Function MSTAT-Miscellaneous Status Register Function MGPIOC-Muxed Gpio Control Function PDMACFG-PCI DMA Configuration Resister Function OBits Description Base Offset Channel RTCCFG-Real Time Clock Configuration Register Function Bits Decode Range Gpio Enable FunctionGpio Base Address Function LPC COM Decode Ranges Function 110 LPC FDD/LPT Decode Ranges Function000 011 11-12 LPC Sound Decode Ranges FunctionLPC Generic Decode Range Function 220 233 240 253 260 273 280 293 1413 Reserved LPC Enables FunctionFirmware Hub FWH Decode Enable Register Reserved. This bit must be a Firmware Hub FWH Select Register DMA Registers Test Mode RegisterDcom-Dma Command Register I/O PCI to LPC I/O Space Registers Dr-Dma Request Register I/O Dcm-Dma Channel Mode Register I/O RWAMB-Read / Write All Mask Bits I/O WSMB-Write Single Mask Bit I/OBit Description Reserved. Must be DBADDR-DMA Base and Current Address Registers I/O Ds-Dma Status Register I/O DCBP-Dma Clear Byte Pointer Register I/O When counting down a DMA transferDBCNT-Dma Base and Current Count Registers I/O DLPAGE-DMA Low Page Registers I/O Dclm-Dma Clear Mask Register I/O 11.2.2.1 Icw1-Initialization Command Word 1 Register I/OInterrupt Controller Registers Dmc-Dma Master Clear Register I/O 11.2.2.3 Icw3-Initialization Command Word 3 Register I/O 11.2.2.2 Icw2-Initialization Command Word 2 Register I/OBit Description Reserved. Must be programmed to all 0s 11-22 11.2.2.4 Icw3-Initialization Command Word 3 Register I/O11.2.2.5 Icw4-Initialization Command Word 4 Register I/O 11.2.2.6 Ocw1-Operational Control Word 1 Register I/O 11.2.2.8 Ocw3-Operational Control Word 3 Register I/O 11.2.2.7 Ocw2-Operational Control Word 2 Register I/O Elcr1-Edge/Level Control Register I/O Bit Decription Counter/Timer RegistersTcw-Timer Control Word Register I/O Elcr2-Edge/Level Control Register I/O 5. When bit 1=0, status and/or count will not be latched Latched. When bit 4=1, the status will not be latched5. When bit 3=0, status and/or count will not be latched 5. When bit 2=0, status and/or count will not be latched TMRCNT-Timer Count Registers I/O TMRSTS-Timer Status Registers I/O Nmisc-Nmi Status and Control Register I/O NMI Registers Used for NMI enabling/disabling. See description in Section NMI Enable. Used by IFB NMI logicReal Time Clock Registers RTCD-Real-time Clock Data Register I/O RTCED-Real-time Clock Extended Data Register I/O Advanced Power Management APM RegistersAPMC-Advanced Power Management Control Port I/O RTCEI-Real-time Clock Extended Index Register I/O Power Management 1 Status APMS-Advanced Power Management Status Port I/OAcpi Registers 11-32 Power Management 1 EnablePower Management 1 Control States can be supported in external logic 3124 Reserved 230 Power Management 1 TimerBit Description Bits Mode General Purpose 0 Status CF9 write General Purpose 0 EnablePower up, this bit is set to ‘1’ 1512 Reserved SMI Registers General Purpose 1 EnableGeneral Purpose 1 Status Thrmsts bit Global Control and EnablePort at B2h in I/O space Status Register is set GPIO7 General Purpose I/O RegistersGlobal Status Register GPIO8 GP Data GP Output Bit is set GP TTL1916 159 Reserved GP Lock GP BlinkGP Invert GP Pull-up GP SMIGP Pulse GP Core 11-42 IDE Controller Register Descriptions PCI Function IDE ConfigurationPCI Configuration Registers Function Configuration Mnemonic Register VGA Palette Snoop. This bit is hardwired to SERR# Enable. This bit is hardwired toWait Cycle Control. This bit is hardwired to Parity Error Response. This bit is hardwired to By writing a 1 to this bit SERR# Status. Read as BMIBA-Bus Master Interface Base Address Register Function MLT-Master Latency Timer Register FunctionBus Master interface registers and correspond to AD154 SID-Subsystem ID Function SVID-Subsystem Vendor ID FunctionIDETIM-IDE Timing Register Function SIDETIM-Slave IDE Timing Register Function Bit Description Reserved DMACTL-Synchronous DMA Control Register Function SDMATIM-Synchronous DMA Timing Register Function Ultra DMA/33 Timing Modes BMICx-Bus Master IDE Command Register I/OUltra DMA/33 Timing Mode Settings IDE Controller I/O Space Registers BMISx-Bus Master IDE Status Register I/O Is equal to the IDE device transfer size Interrupt/Activity Status Combinations312 12-12 PCI Configuration Registers-Function Universal Serial Bus USB ConfigurationUsbren Bit Description 1510 Reserved. Read USB Host Controller Register Descriptions PCI FunctionReserved. Read as Reserved. Read as 0’s Resets STA to 0 by writing a 1 to this bit Register in Function This field13-4 INTLN-Interrupt Line Register Function USBBA-USB I/O Space Base Address Function LEGSUP-Legacy Support Register Function INTPN-Interrupt Pin FunctionMiscellaneous Control Function SBRNUM-Serial Bus Release Number Function Accesses that are part of the sequence Default to 1 for compatibility with older USB softwareNeeds to be serviced later Appropriate enable bits are set USBCMD-USB Command Register I/O USBREN-USB Resume EnableUSB Host Controller I/O Space Registers By Software or Hardware Run/Stop, Debug Bit InteractionSwdbg Bit Run/Stop Bit Operation Stop=0, the Frnum register can be reprogrammed Register = USBINTR-USB Interrupt Enable Register I/OUSBSTS-USB Status Register I/O Interrupt is generated to the system SOFMOD-Start of Frame SOF Modify Register I/O Address signalsFRNUM-Frame Number Register I/O FLBASEADD-Frame List Base Address Register I/O PORTSC-Port Status and Control Register I/O Register define the hub states as follows X0 DisableAsserted, the corresponding port is disabled EOF2 time See of the USB Specification 13-14 Base Address Register SM Bus Controller ConfigurationSM Bus Configuration Registers Function Class Code 0C-1Fh Reserved Shutdown special cycle System Management Register Descriptions14-2 STA to 0 by writing a 1 to this bit 14-4 SMBBA-SMBus Base Address Function Interrupt pin PIRQB# is used Host Configuration Smbshdw2-SMBus Slave Shadow Port 2 Function Smbslvc-SMBus Slave Command FunctionSMBus I/O Space Registers Smbshdw1-SMBus Slave Shadow Port 1 Function Position Transaction errors are caused bySmbhststs-SMBus Host Status Register I/O Smbslvsts-SMBus Slave Status Register I/O Smbhstcnt-SMBus Host Control Register I/O Smbhstdat0-SMBus Host Data 0 Register I/O Smbhstcmd-SMBus Host Command Register I/OCommand field of SMBus host transaction Smbhstadd-SMBus Host Address Register I/O Smbblkdat-SMBus Block Data Register I/O Smbhstdat1-SMBus Host Data 1 Register I/OSmbslvcnt-SMBus Slave Control Register I/O Address 10h or one of the slave shadow port addresses 14.3.9.1 Smbshdwcmd -SMBus Shadow Command Register I/OSmbslvdat-SMBus Slave Data Register I/O 14.3.9.2 10.3.11.smbslvevt-SMBus Slave Event Register I/O 14-12 PCI Interface PCI/LPC Bridge DescriptionInterrupt Controller Programming the Interrupt Controller Initialization Command Words ICWs15-2 End of Interrupt EOI Operation Command Words OCWsAutomatic End of Interrupt Aeoi Mode End of Interrupt Operation Automatic Rotation Equal Priority Devices Fully Nested ModeSpecial Fully Nested Mode Modes of Operation Poll Command Cascade ModeSpecific Rotation Specific Priority Masking on an Individual Interrupt Request Basis Edge and Level Triggered ModeSpecial Mask Mode Interrupt Masks Interrupt Steering Reading the Interrupt Controller Status Protocol Quiet Active ModeContinuous Idle Mode Serial Interrupts 3222 Stop FrameSerirq Frames Data Frame Number Usage # Clocks Past Start Programming the Interval Timer Timer/Counters15-10 Write Operations Interval Timer Control Word Format 15-12 Counter Latch CommandRead Operations Counter I/O Port Read Real Time Clock Read Back Command RTC Standard RAM Bank RTC Registers and RAMIndex Address Name 1 Invalid 0 Invalid 15.5.1.1 Register a90625 ms 8125 ms 15.5.1.3 Register C 15.5.1.2 Register BRSMRST# 15.5.1.4 Register D RTC Update CycleRTC Interrupts Lockable RAM Ranges 15-18 Acpi State Description IFB Power ManagementIFB Power States and Consumption Overview Causes of SMI# IFB Power PlanesPower Plane Descriptions 16.2.2 SMI# Generation SCI Event Comment SCI GenerationSleep States Causes of SCI# Offset Register Name/Function Comment Acpi Bits Not Implemented by IFBEntry/Exit for the S4 and S5 States Acpi Bits Not Implemented in IFB Action after Power Returns Handling of Power Failures in IFBS5 Wake Event Comment 16-6