Data Integrity and Error Handling

•‘Load’ Overlapping ‘Forward’. Set when the SDC is doing a ‘Forward’ by sending data to the MDC and the MDC starts to send the SDC data before the ‘Forward’ is complete.

•‘Forward’ overlapping ‘Load’. Set when the SDC is receiving data from the MDC, and then is told to send data to the MDC at the same time it is receiving data.

6.5.6SDC/System Bus Errors

•LEN# Protocol Error. Set when the actual write data received not matching length given by the system bus transaction. Set when the processor transfers either more or less data than is indicated by the LEN# encoding on the bus transaction.

•Write Data Protocol Error. Set when data is received from processor without a TRDY# having been given. Set when the processor places data on the bus without the correct TRDY# assertion. This may be for writes or implicit writebacks. It is also set if the processor drives a DRDY# on a zero-length write transaction.

•DRDY# Protocol Error. This error occurs and is flagged if a) DRDY# is not deasserted 1 clock after DBSY# deassertion OR b) DRDY# is not deasserted 2 clocks after SBUSY# deassertion. Either of these implies that the processor is holding onto the data bus longer than it is supposed to.

6.5.7SDC Internal Errors

The SDC has two internal error bits that it detects.

•Data Buffer Parity Error. This is set when the data buffer detects a parity error on data that was placed into the buffer as good. Data with uncorrectable errors, such as double-bit ECC errors or data parity errors from the private bus, is placed in the buffer with good parity and has a bit set to indicate that the data is uncorrectable. If the data is read out of the buffer and parity is bad, then an internal alpha-hit or other error occurred.

•Simultaneous write-one-to-clear and hardware set. When the SDC_FERR register is set, it can only be cleared by writing a one to the set bit. If on the cycle that SDC_FERR is cleared, there is an error for that same bit, then 2 things happen a) the bit is set to a one and behaves as normal and b) the Simultaneous Clear and Set error bit is set. This bit indicates that there was not time to reset the logging registers associated with the incoming error, so that the log registers are stale and cannot be considered as valid.

If software is writing a single one to the unique asserted bit in SDC_FERR, then the Simultaneous bit is only set if the new error is to the bit being cleared by software. If software is clearing the register by writing all 1’s to every location, then any new incoming error will also set the simultaneous bit. Software should only write to the single location (or locations) that it wishes to clear, and not write all 1’s to the entire register.

6.6Error Determination

The status registers listed in Table 6-1show which error occurred. Many of the errors also capture the actual error. This is listed under ‘Log Register’. Parity or ECC errors generally capture the data and the parity/ECC bits for the failing transfer. This information can be used for debug and diagnostic purposes. The log register is updated when the appropriate bit is set in the status register. Only after the status register (FERR register) is cleared will a new value be captured on subsequent errors.

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Intel® 460GX Chipset Software Developer’s Manual