Register Descriptions

3Inbound Delayed Read Time-out Flag

Each inbound read request that is accepted and serviced as a delayed read (i.e. the PXB retries the request) will initiate a watchdog timer (215 cycles, per the PCI spec). If the data has been returned and the timer expires before the requesting master initiates its repeat request, this flag will be set. This flag may be configured to assert SERR# or PERR# in the ERRCMD register. This bit remains set until explicitly cleared by software writing a 1 to this bit.

2reserved(0)

1Performance Monitor #1 Event Flag

This flag is set when the Performance Monitor #1 requests that an interrupt request be asserted. The PME and PMR registers (Section 2.5.3.3, Section 2.5.3.2) describe the conditions that can cause this to occur. While this bit is set, the INT(A,B)RQ# line will be asserted. This bit remains set until explicitly cleared by software writing a 1 to this bit.

0Performance Monitor #0 Event Flag

This flag is set when the Performance Monitor #0 requests that an interrupt request be asserted. The PME and PMR registers (Section 2.5.3.3, Section 2.5.3.2) describe the conditions that can cause this to occur. While this bit is set, the INT(A,B)RQ# line will be asserted. This bit remains set until explicitly cleared by software writing a 1 to this bit.

2.4.4.2ERRCMD: Error Command Register

Address Offset:

46h

Size:

8 bits

Default Value:

00h

Attribute:

Read/Write

This register provides extended control over the assertion of SERR# beyond the basic controls specified in the PCI-standard PCICMD register.

Bits Description

7reserved(0)

6Assert SERR# on Observed Parity Error

If set, the PXB asserts SERR# if PERR# is observed asserted, and the PXB was not the asserting agent.

5Assert SERR# on Received Data with Parity Error

If set, the PXB asserts SERR# upon receiving PCI data (i.e. an inbound write or outbound read) with a parity error. This occurs regardless of whether PXB asserts it’s PERR# pin.

4Assert SERR# on Address Parity Error

If set, the PXB asserts SERR# on detecting a PCI address parity error.

3Assert PERR# on Data Parity Error

If set, and the PERRE bit is set in the PCICMD register, the PXB asserts PERR# upon receiving PCI data with parity errors.

2Assert SERR# on Inbound Delayed Read Time-out

Each inbound read request that is accepted and serviced as a delayed read (i.e. the PXB retries the request) will initiate a watchdog timer (215 cycles, per the PCI spec). If this enable is set, the PXB will assert SERR# if the data has been returned and the timer expires before the requesting master initiates its repeat request. Default=0.

1reserved(0)

0Return Hard Fail Upon Generating Master Abort

If set, the PXB will return a Hard Fail response through the SAC to the system bus after generating a master abort time-out for an outbound transaction placed on the PCI bus. If cleared, the PXB will return a normal response (with data of all 1’s for a read). In either case, an error flag is set in the PCISTS register. Default=0.

Intel® 460GX Chipset Software Developer’s Manual

2-23