Register a, Invalid 0 Invalid, 90625 ms 8125 ms | Intel 460GX

PCI/LPC Bridge Description

The extended RAM bank is also accessed using an indexed scheme. I/O address 72h is used as the address pointer and I/O address 73h is used as the data register. Index addresses above 127h are not valid.

15.5.1.1	Register A
	Address Offset:	0Ah
	Default Value:	NA - This register is not affected by any system reset signal.
	Attribute:	Read/Write

This register is used for general configuration of the RTC Functions.

Bit(s)							Description

7	UPDATE IN PROGRESS (UIP): This bit may be monitored as a status flag. When asserted as a 1,
	the update is soon to occur or is in progress. If 0, the update cycle will not start for at least 244 µs.
	The time, calendar, and alarm information in RAM is always available when the UIP bit is 0.

6:4	Division Chain Select (DVx): These three bits control the divider chain for the oscillator.
	DV2 DV1 DV0 Function
	0 1 0 Normal Operation
	1 1 X Divider Reset
	1 0 1 Bypass 15 stages (test mode only)
	1 0 0 Bypass 10 stages (test mode only)
	0 1 1 Bypass 5 stages (test mode only)
	0 1 1 Invalid
	0 0 0 Invalid

3:0	Rate Select Bits (RSx): Selects one of 13 taps of the 15 stage divider chain. The selected tap can
	generate a periodic interrupt if the PIE bit is set in register B. Otherwise this tap will set the PF flag
	of register C. If the periodic interrupt is not to be used, these bits should all be set to zero.

		RS3		RS2	RS1		RS0	Periodic Rate

		0		0	0		0	Interrupt never toggles

		0		0	0		1	3.90625 ms

		0		0	1		0	7.8125 ms

		0		0	1		1	122.070 ∝	s

		0		1	0		0	244.141 ∝	s

		0		1	0		1	488.281 ∝	s

		0		1	1		0	976.5625∝ s

		0		1	1		1	1.953125 ms

		1		0	0		0	3.90625 ms

		1		0	0		1	7.8125 ms

		1		0	1		0	15.625 ms

		1		0	1		1	31.25 ms

		1		1	0		0	62.5 ms

		1		1	0		1	125 ms

		1		1	1		0	250 ms

		1		1	1		1	500 ms

Intel® 460GX Chipset Software Developer’s Manual

15-15

Image 285

Intel 460GX manual Register a, Invalid 0 Invalid, 90625 ms 8125 ms

Contents

Intel 460GX Chipset System Software Developer’s Manual Intel 460GX Chipset System Software Developer’s Manual Contents Coherency 10.1 Latency 10-1 11-8 13.2.4 Figures Tables 12-11 System Overview Introduction Component Overview Intel 460GX Chipset ComponentsName Function Itanium Processor System Bus Support Product Features PXB Features Dram Interface SupportI/O Support GXB Features RAS Features Reference Documents Other Platform Components1 I/O & Firmware Bridge IFB Programmable Interrupt Device PID Date Description June Initial release Revision History Introduction Register Descriptions Access Mechanism Partitioning Access RestrictionsDevice Mapping on Bus CBN Device Register Attributes Default Upon ResetReserved Bits Defined in Registers Reserved or Undefined Register Locations I/O Mapped Registers Configaddress Configuration Address RegisterConsistency Gart Programming Region Configdata Configuration Data Register Error Handling Registers1 SAC 1.1 1.2 Bits Description Disable1.3 Valid Ferrsac First Error Status Register Nerrsac All Error Status Register Biuitid BIU Itid Register Saferr System Address on First Error Address bits Biudata BIU Data Register 2.1 SEC0DFERR Data on First Memory Card B SEC 2 SDC2.2 SEC0ECCFERR ECC on First Memory Card B SEC 2.3 SEC0TXINFOFERR Txinfo on First Memory Card B SEC 2.5 DED0ECCFERR ECC on First Memory Card B DED 2.4 DED0DFERR Data on First Memory Card B DED2.6 DED0TXINFOFERR Txinfo on First Memory Card B DED 2.7 SEC1DFERR Data on First Memory Card a SEC 2.8 SEC1ECCFERR ECC on First Memory Card a SEC 2.9 SEC1TXINFOFERR Txinfo on First Memory Card a SEC2.10 DED1DFERR Data on First Memory Card a DED Sdcferr First Error Status Register 2.11 DED1ECCFERR ECC on First Memory Card a DED2.12 DED1TXINFOFERR Txinfo on First Memory Card a DED 21 ’Forward’ Underflow Card a Left Stack Error FL1 22 ’Forward’ Underflow Card a Right Stack Error FR115 ’Forward’ Underflow Card B Right Stack Error FR0 14 ’Forward’ Underflow Card B Left Stack Error FL0 Sdcnerr SDC Next Error Status Register Pcmdferr Command on First Pcmd Parity ErrorPitidferr Data on First Pitid Parity Error Sdcrspferr Response on First Sdcrsp Error Dpbrleferr Private Data Bus Receive Length ErrorECCMSK0 ECC Mask Register Card B ParMskP PB Parity Mask and IB Correction Enable Register ECCMSK1 ECC Mask Register Card aEccmskf ECC Mask Register Pvddferr Data on First PVD Parity Error Pvdparferr Parity on First PVD Parity ErrorPvdtxinfoferr Txinfo on First PVD Parity Error Secfeccferr ECC on First System Bus SEC Secfdferr Data on First System Bus SECSecftxinfoferr Txinfo on First System Bus SEC Dedfdferr Data on First System Bus DED Que-Overflow Error Ferrmac First Error Status Register3 MAC Dedfeccferr ECC on First System Bus DED Cmndferr Command on First Error Errsts Error Status Register4 PXB Errcmd Error Command Register 5 GXB Ferragp First Error Status Register for AGP5.1 Ferrpci Nerragp Next Errors Status Register for AGP Ferrgart First Error Status Register for Gart Pacerr PCI Address & Cmd First Error Pderr PCI Data First ErrorNerrgart Fepci Register Records an PCI Bus Error Flag Nepci Register Records an PCI Bus Error Flag6 WXB Bits Description Intrq Asserted Flag Fepci PCI Bus First Error Status Register Nepci PCI Bus Next Error Status Register Fepcidl PCI First Error Data Log Fepcial PCI First Error Address/Command LogPerformance Monitor Registers 6764 C/BE30 6332 AD6332 310 AD310 Count Value OverflowLength Encodings Dmask Encodings Event Select Umask Encodings Disable Source Enable SourceReload Control 2 SDC FSBDPMD1,0 System Bus Performance Monitor Data Registers 3 PXB 3.1 PMD10 Performance Monitoring Data Register3.2 PMR10 Performance Monitoring Response 3.3 PME10 Performance Monitoring Event Selection Reload ModeCount Data Cycles Initiating Agent Selection AGPPMD0,1 AGP Performance Monitor Data Registers 4 GXB Pcipmd PCI Performance Monitor Data Registers Percon Performance Monitor Control RegisterEvent 1 Input AGPPMC0,1 AGP Performance Monitor Configuration Register Event 0 InputPipe or Sideband Request Mask Pcipmc PCI Performance Monitor Configuration Register EVENT1 Count EnableInitiating Agent Disable Source 5 WXB PCIWXBPMC0 PCI Performance Monitor Configuration RegisterData Transfer and Transaction Qualifier Issuing Agent Qualifier PCIWXBPMC1 PCI Performance Monitor Configuration Register Interrupt Related RegistersXtprs External Task Priority Registers PID PCI Memory-mapped Registers Address Name Access Default Value2.1 I/O Register Select Register FEC00000h Memory-Mapped Register Summary 2.2 I/O Window Register FEC00010h PID Indirect Access RegistersXAPIC EOI Register FEC00040h I/O Window Register Format Offset Name Access Default Value 3.1 I/O xAPIC ID Register 00hRTE Memory-mapped Register Summary Cont’d 3.3 I/O xAPIC Arbitration ID Register 02h 3.2 I/O xAPIC Version Register 01hI/O Apic ID Register Format I/O xAPIC Version Register Format 3.4 I/O xAPIC RTE 10h-8Fh Bits Sapic Mode Apic Mode Description NameI/O xAPIC Arbitration ID Register Format 10. I/O xAPIC RTE Format 10. I/O xAPIC RTE Format Cont’d Sapic Mode Apic Mode Description Name Vector Destination System Architecture CoherencyProcessor Coherency Ordering PCI CoherencyAGP Coherency WXB Arbitration WXB Arbitration at the PCI BusArbitration for Inbound Transactions Indivisible Operations Big-endian SupportProcessor Locks Arbitration for Outbound Transactions Atomic Writes Inbound PCI LocksAtomic Reads Locks with AGP Non-coherent Traffic WXB PCI Hot-Plug Support Interrupt Delivery Slot Power-down and Disable Slot Power-up and Enable System Architecture System Address Map Memory MapCompatibility Region System Memory Address Space System Firmware Medium Extended Memory Region Low Extended Memory Region High Extended Memory above 4G Re-mapped Memory AreasVariable GAP Itanium Processor and Chipset-specific Memory Space I/O Address Map System I/O Address Space High PXB must ignore GXB must BINIT# after Gart Devices View of the System Memory Map Legal and Illegal Address Disposition Address DispositionAddress Range Outbound Inbound Dest. Decision Main memory if present above 4 GB Address Disposition Cont’dAbove TOM Binit System Address Map Memory Subsystem General Memory CharacteristicsOrganization System Maximum Memory Configuration Using Two Cards Technology & Configuration Size Minimum/Maximum Memory Size per ConfigurationDimm Types Double Number Memory Size Address Interleaving Interleaving/Configurations Summary of Configuration Rules Non-uniform Memory ConfigurationsBandwidth Memory Subsystem Clocking Supporting FeaturesAuto Detection Removing a Bad Row Memory Scrubbing Hardware InitializationScrubbing Time Memory Size Time to Scrub Memory Subsystem Data Integrity and Error Handling IntegritySystem Bus Expander Buses DramPCI Buses 5 AGP Usage of First-error and Next-error Memory ECC RoutingData Poisoning Masked Bits BERR#/BINIT# GenerationINTREQ# Data ECC or Parity Errors SAC/SDC ErrorsXBINIT# XSERR# SAC to SDC Interface Errors System Bus Errors 5 SDC/Memory Card Interface Errors SAC to MAC Interface Errors Error Determination 6 SDC/System Bus ErrorsSDC Internal Errors SAC Address on an Error Special Notes on Usage of SECTID, DEDTID, Fsetid Registers SDC Logging Registers Clearing Errors Multiple Errors1 SAC/SDC Error Clearing ERR ERR SDC Multiple Errors SAC Multiple Errors Single Errors with Multiple ReportingError Anomalies SAC Error Flow on Data Data Flow Errors Table of Errors Error Conditions Error Cases SAC to SDC Interface ErrorsSystem Bus ADD/CMND Error Cases Cont’d Internal SDC Error Detected as PCI Master PXB Errors PCI Bus Monitoring PCI IntegrityPXB as Master Master Abort PXB as Target GXB Error Flow Target RetryTarget Abort GXB Errors GXB Error Signals Gart Interface Errors GXB Error Flow Multiple Errors Usage of First Error and Next Error Registers WXB Data Integrity and Error HandlingIntegrity Data Parity Poisoning Error Steering/Signaling Error Mask BitsSupported Error Escalation to XBINIT#a Abbreviation Error Supported Error Escalation to PA/BINTRQ# Supported Error Escalation to SERROUT#aSERR# Generation Escalation Error Determination and Logging INTRQ# InterruptXBINIT# Generation WXB as Bus Master Error Conditions Other Violations WXB as Target PCI Interface Errors System Error SignaledDiscard Timer Expiration Graphics Address Relocation Table Gart AGP Subsystem 24b 12b22b 14b Gart Entry Format for 4kB Pages Gart Implementation Sizes Programming GartGtlb Parity Coherency SGW#SE2 ADSC# ADSP# ADV# LBO# SB# SW# AGP Traffic 4.1 3.3V AGP 1X and 2X Mode CompatibilityInterrupt Handling Addresses Used by the Graphics Card Coherency, Translation and Types of AGP Traffic Traffic Priority Ordering Rules Processor Locks and AGP TrafficCoherency for AGP/PCI Streams Address Alignment and Transfer Sizes Address FaultsPCI Semantics Traffic Inbound Reads Inbound Delayed Read Matching Rules PCI Stream Read PrefetchingInbound Reads Directed To Memory Command Address BEs Delayed Read Matching CriteriaInbound I/O Reads Inbound Writes Retry/Disconnect Conditions Outbound ReadsOutbound Writes Fast Back-to-Back Transactions Transfer Data Length Combining Supported Used ModeBurst Write Combining Modes 1st write 2nd write 3rd write Transferred as GXB Address Map LatencyInbound Read Prefetching Bandwidth Estimates for Various Request Sizes AGP Subsystem AGP Subsystem WXB Hot-Plug Ihpc Configuration Registers Ihpc Configuration Register Space Number List for the Ihpc PCI Register Descriptions VID Vendor Identification RegisterDid Device Identification Register Pcicmd PCI Command Register RID Revision Identification Register Pcists PCI Status Register Class Class Register MLT Master Latency Timer RegisterCLS Cache Line Size HDR Header Register Svid Subsystem Vendor Identification Base AddressSID Subsystem ID Interrupt Line Miscellaneous Hot-Plug Configuration Interrupt PinHot-Plug Slot Identifier Hot-Plug Features Switch Change Serr StatusPower Fault Serr Status Memory Mapped Register Access Port Memory Access IndexIhpc Memory Mapped Registers Arbiter Serr Status M66EN Ihpc Memor Mapped Register Space Number List for Ihpc Memory Mapped Register Descriptions Slot Enable LED Control Hot-Plug Miscellaneous Hot-Plug Interrupt Input and Clear Hot-Plug Interrupt Mask Serial Input Byte Data Serial Input Byte Pointer General Purpose OutputHot-Plug Non-interrupt Inputs Hot-Plug Switch Interrupt Redirect Enable Slot Power ControlExtended Hot-Plug Miscellaneous PCI Configuration Registers Function PCI / LPC / FWH ConfigurationMnemonic Register Register Access IFB Register Mapping Pcists BiosenClassc Hedt PCI Configuration Registers-Function 1 IDE Interface IDE Configuration Universal Serial Bus USB Configuration PCI Configuration Registers-Function 2 USB InterfaceConfiguration Offset Mnemonic Register SMBus Configuration Registers Function SMBus Controller Configuration IFB Register Mapping Usage of the SW SMI# Timer Usage of 1MIN Timer in Power ManagementCD-ROM Auto RUN Feature of the OS IFB Usage Considerations Reserved Secondary Primary Drive Ultra DMA Mode Enable Ultra DMA ConfigurationDisabled Enabled SSDE1 SSDE0 PSDE1 PSDE0 Overview Determining a Drive’s Transfer Rate CapabilitiesCapability Word Bits Field Offset Ultra DMA Fields that Indicate Ultra DMA Drive Capabilities Capability Word Bits DMAPIO Capability Word Bits Field Determining a Drive’s Best Ultra DMA Capability Capability Word Offset Bits Field 150 Minimum Multi Word DMA Transfer Cycle Time per10-6 Determining a Drive’s Best PIO Capability Drives Reported DMA Drive’s Best DMA Mode Cycle Time Drive PIO Capability as a Function of Cycle Time Drives Reported PIO Drive’s Best PIO Mode 10.5.6.1 DMA/PIO Timing Settings IFB Timing SettingsIFB Drive Mode Based on DMA/PIO Capabilities Mode Yes Disabled Enabled DMA Mode Iordy If fixed disk DMA Iordy IDE Ultra DMA Timing Settings Drive Configuration for Selected Timings10. Ultra DMA Timing Value Based on Drive Mode DMA/PIO Timing Values Based on Piix Cable Mode/System Speed 12. PIO Transfer/Mode Values Drive’s Selected PIO Speed Capability10-12 13. Drive Capabilities Checklist Settings Checklist Example #1 Ultra DMA/33 Configuration Example Configurations14. IFB Settings Checklist Register Type Offset Value Comments 40-41h E377h Mode config. for Primary IDE Timing Register Example #3 Non Ultra DMA/33 Drive Configuration4A-4Bh 0002h Ultra DMA mode config 44h 0Bh Ultra DMA Control Register Ultra DMA System Software Considerations 4A-4Bh 0000h10-16 Intel 460GX Chipset Software Developer’s Manual 10-17 BMISX-Bus Master IDE Status Register I/O Bit Description Reserved. This bit is hardwired toBit Description Completed or halted Bit Type Description USB Resume Enable Bit 10-20 LPC/FWH Interface Configuration VID-Vendor Identification Register FunctionDID-Device Identification Register Function PCISTS-PCI Device Status Register Function PCICMD-PCI Command Register Function CLASSC-Class Code Register Function RID-Revision Identification Register FunctionHEDT-Header Type Register Function Bit Acpi Enable Function Acpi Base Address FunctionSCI IRQ Routing Control PIRQRCAD-PIRQx Route Control Registers Function BIOSEN-BIOS Enable Register Function TOM-Top of Memory Register Function SerIRQC-Serial IRQ Control Register Function Deterministic Latency Control Register Function MSTAT-Miscellaneous Status Register Function PDMACFG-PCI DMA Configuration Resister Function O MGPIOC-Muxed Gpio Control FunctionBits Description Base Offset Channel RTCCFG-Real Time Clock Configuration Register Function Gpio Base Address Function Gpio Enable FunctionLPC COM Decode Ranges Function Bits Decode Range 000 LPC FDD/LPT Decode Ranges Function011 110 LPC Generic Decode Range Function LPC Sound Decode Ranges Function220 233 240 253 260 273 280 293 11-12 Firmware Hub FWH Decode Enable Register LPC Enables FunctionReserved. This bit must be a 1413 Reserved Firmware Hub FWH Select Register Dcom-Dma Command Register I/O Test Mode RegisterPCI to LPC I/O Space Registers DMA Registers Dr-Dma Request Register I/O Dcm-Dma Channel Mode Register I/O WSMB-Write Single Mask Bit I/O RWAMB-Read / Write All Mask Bits I/OBit Description Reserved. Must be DBADDR-DMA Base and Current Address Registers I/O Ds-Dma Status Register I/O DBCNT-Dma Base and Current Count Registers I/O When counting down a DMA transferDLPAGE-DMA Low Page Registers I/O DCBP-Dma Clear Byte Pointer Register I/O Interrupt Controller Registers 11.2.2.1 Icw1-Initialization Command Word 1 Register I/ODmc-Dma Master Clear Register I/O Dclm-Dma Clear Mask Register I/O 11.2.2.2 Icw2-Initialization Command Word 2 Register I/O 11.2.2.3 Icw3-Initialization Command Word 3 Register I/OBit Description Reserved. Must be programmed to all 0s 11.2.2.5 Icw4-Initialization Command Word 4 Register I/O 11.2.2.4 Icw3-Initialization Command Word 3 Register I/O11.2.2.6 Ocw1-Operational Control Word 1 Register I/O 11-22 11.2.2.8 Ocw3-Operational Control Word 3 Register I/O 11.2.2.7 Ocw2-Operational Control Word 2 Register I/O Elcr1-Edge/Level Control Register I/O Tcw-Timer Control Word Register I/O Counter/Timer RegistersElcr2-Edge/Level Control Register I/O Bit Decription 5. When bit 3=0, status and/or count will not be latched Latched. When bit 4=1, the status will not be latched5. When bit 2=0, status and/or count will not be latched 5. When bit 1=0, status and/or count will not be latched TMRCNT-Timer Count Registers I/O TMRSTS-Timer Status Registers I/O Nmisc-Nmi Status and Control Register I/O NMI Registers Real Time Clock Registers NMI Enable. Used by IFB NMI logicRTCD-Real-time Clock Data Register I/O Used for NMI enabling/disabling. See description in Section APMC-Advanced Power Management Control Port I/O Advanced Power Management APM RegistersRTCEI-Real-time Clock Extended Index Register I/O RTCED-Real-time Clock Extended Data Register I/O APMS-Advanced Power Management Status Port I/O Power Management 1 StatusAcpi Registers Power Management 1 Control Power Management 1 EnableStates can be supported in external logic 11-32 Bit Description Bits Mode Power Management 1 TimerGeneral Purpose 0 Status 3124 Reserved 230 Power up, this bit is set to ‘1’ General Purpose 0 Enable1512 Reserved CF9 write General Purpose 1 Enable SMI RegistersGeneral Purpose 1 Status Port at B2h in I/O space Global Control and EnableStatus Register is set Thrmsts bit Global Status Register General Purpose I/O RegistersGPIO8 GPIO7 GP Data GP Output 1916 GP TTL159 Reserved Bit is set GP Blink GP LockGP Invert GP Pulse GP SMIGP Core GP Pull-up 11-42 PCI Configuration Registers Function IDE ConfigurationConfiguration Mnemonic Register IDE Controller Register Descriptions PCI Function Wait Cycle Control. This bit is hardwired to SERR# Enable. This bit is hardwired toParity Error Response. This bit is hardwired to VGA Palette Snoop. This bit is hardwired to By writing a 1 to this bit SERR# Status. Read as MLT-Master Latency Timer Register Function BMIBA-Bus Master Interface Base Address Register FunctionBus Master interface registers and correspond to AD154 SVID-Subsystem Vendor ID Function SID-Subsystem ID FunctionIDETIM-IDE Timing Register Function SIDETIM-Slave IDE Timing Register Function Bit Description Reserved DMACTL-Synchronous DMA Control Register Function SDMATIM-Synchronous DMA Timing Register Function Ultra DMA/33 Timing Mode Settings BMICx-Bus Master IDE Command Register I/OIDE Controller I/O Space Registers Ultra DMA/33 Timing Modes BMISx-Bus Master IDE Status Register I/O Interrupt/Activity Status Combinations Is equal to the IDE device transfer size312 12-12 Universal Serial Bus USB Configuration PCI Configuration Registers-FunctionUsbren USB Host Controller Register Descriptions PCI Function Bit Description 1510 Reserved. ReadReserved. Read as Reserved. Read as 0’s Resets STA to 0 by writing a 1 to this bit This field Register in Function13-4 INTLN-Interrupt Line Register Function USBBA-USB I/O Space Base Address Function Miscellaneous Control Function INTPN-Interrupt Pin FunctionSBRNUM-Serial Bus Release Number Function LEGSUP-Legacy Support Register Function Needs to be serviced later Default to 1 for compatibility with older USB softwareAppropriate enable bits are set Accesses that are part of the sequence USBREN-USB Resume Enable USBCMD-USB Command Register I/OUSB Host Controller I/O Space Registers Swdbg Bit Run/Stop Bit Operation Run/Stop, Debug Bit InteractionStop=0, the Frnum register can be reprogrammed By Software or Hardware USBSTS-USB Status Register I/O USBINTR-USB Interrupt Enable Register I/OInterrupt is generated to the system Register = FRNUM-Frame Number Register I/O Address signalsFLBASEADD-Frame List Base Address Register I/O SOFMOD-Start of Frame SOF Modify Register I/O PORTSC-Port Status and Control Register I/O Asserted, the corresponding port is disabled X0 DisableEOF2 time See of the USB Specification Register define the hub states as follows 13-14 SM Bus Configuration Registers Function SM Bus Controller ConfigurationClass Code 0C-1Fh Reserved Base Address Register System Management Register Descriptions Shutdown special cycle14-2 STA to 0 by writing a 1 to this bit 14-4 SMBBA-SMBus Base Address Function Interrupt pin PIRQB# is used Host Configuration SMBus I/O Space Registers Smbslvc-SMBus Slave Command FunctionSmbshdw1-SMBus Slave Shadow Port 1 Function Smbshdw2-SMBus Slave Shadow Port 2 Function Smbhststs-SMBus Host Status Register I/O Transaction errors are caused bySmbslvsts-SMBus Slave Status Register I/O Position Smbhstcnt-SMBus Host Control Register I/O Command field of SMBus host transaction Smbhstcmd-SMBus Host Command Register I/OSmbhstadd-SMBus Host Address Register I/O Smbhstdat0-SMBus Host Data 0 Register I/O Smbhstdat1-SMBus Host Data 1 Register I/O Smbblkdat-SMBus Block Data Register I/OSmbslvcnt-SMBus Slave Control Register I/O Smbslvdat-SMBus Slave Data Register I/O 14.3.9.1 Smbshdwcmd -SMBus Shadow Command Register I/O14.3.9.2 10.3.11.smbslvevt-SMBus Slave Event Register I/O Address 10h or one of the slave shadow port addresses 14-12 PCI/LPC Bridge Description PCI InterfaceInterrupt Controller Initialization Command Words ICWs Programming the Interrupt Controller15-2 Automatic End of Interrupt Aeoi Mode Operation Command Words OCWsEnd of Interrupt Operation End of Interrupt EOI Special Fully Nested Mode Fully Nested ModeModes of Operation Automatic Rotation Equal Priority Devices Cascade Mode Poll CommandSpecific Rotation Specific Priority Special Mask Mode Edge and Level Triggered ModeInterrupt Masks Masking on an Individual Interrupt Request Basis Interrupt Steering Reading the Interrupt Controller Status Continuous Idle Mode Quiet Active ModeSerial Interrupts Protocol Serirq Frames Stop FrameData Frame Number Usage # Clocks Past Start 3222 Timer/Counters Programming the Interval Timer15-10 Write Operations Interval Timer Control Word Format Read Operations Counter Latch CommandCounter I/O Port Read 15-12 Real Time Clock Read Back Command RTC Registers and RAM RTC Standard RAM BankIndex Address Name 15.5.1.1 Register a 1 Invalid 0 Invalid90625 ms 8125 ms 15.5.1.2 Register B 15.5.1.3 Register CRSMRST# RTC Interrupts RTC Update CycleLockable RAM Ranges 15.5.1.4 Register D 15-18 IFB Power States and Consumption IFB Power ManagementOverview Acpi State Description Power Plane Descriptions IFB Power Planes16.2.2 SMI# Generation Causes of SMI# Sleep States SCI GenerationCauses of SCI# SCI Event Comment Entry/Exit for the S4 and S5 States Acpi Bits Not Implemented by IFBAcpi Bits Not Implemented in IFB Offset Register Name/Function Comment Handling of Power Failures in IFB Action after Power ReturnsS5 Wake Event Comment 16-6