Intel 460GX 12.2.5CLASSC–ClassCode Register (Function 1), 12.2.4PCISTS–PCIDevice Status Register (Function 1)

IDE Configuration

12.2.4PCISTS–PCI Device Status Register (Function 1)

Address Offset:	06–07h
Default Value:	0280h
Attribute:	Read/Write

PCISTS is a 16-bit status register for the IDE interface Function. The register also indicates the IFB's DEVSEL# signal timing.

Bit	Description
15	Detected Parity Error. Read as 0.
14	SERR# Status. Read as 0.
13	Master-Abort Status (MAS)–R/WC.When the Bus Master IDE interface Function, as a master,
	generates a master abort, MAS is set to a 1. Software sets MAS to 0 by writing a 1 to this bit.
12	Received Target-Abort Status (RTA)–R/WC.When the Bus Master IDE interface Function is a
	master on the PCI Bus and receives a target abort, this bit is set to a 1. Software sets RTA to 0
	by writing a 1 to this bit.
11	Signaled Target Abort Status (STA)–R/WC.This bit is set when the IFB IDE interface Function
	is targeted with a transaction that the IFB terminates with a target abort. Software resets STA to
	0 by writing a 1 to this bit.
10:9	DEVSEL# Timing Status (DEVT)–RO.For the IFB, DEVT=01 indicating medium timing for
	DEVSEL# assertion when performing a positive decode. DEVSEL# timing does not include
	configuration cycles.
8	Data Parity Detected (DPD). Read as 0.
7	Fast Back to back Capable (FBC)–RO. Hardwired to a 1.
6:0	Reserved.

12.2.5CLASSC–Class Code Register (Function 1)

Address Offset:	09-0Bh
Default Value:	010180h
Attribute:	Read only

This register identifies the Base Class Code, Sub-Class Code, and Device Programming interface for IFB PCI Function 1.

Bit Description

23:16 Base Class Code (BASEC). 01h=Mass storage device.

15:8 Sub-Class Code (SCC). 01h=IDE controller.

7:0 Programming Interface (PI). 80h=Capable of IDE bus master operation.

Intel® 460GX Chipset Software Developer’s Manual 12-3