IFB Usage Considerations

Interrupt/Activity Status Combinations

Bit 2

Bit 0

Description

 

 

 

0

1

DMA transfer is in progress. No interrupt has been generated by the IDE device.

 

 

 

1

0

The IDE device generated an interrupt and the Physical Region Descriptors

 

 

exhausted. This is normal completion where the size of the physical memory regions is

 

 

equal to the IDE device transfer size.

 

 

 

1

1

The IDE device generated an interrupt. The controller has not reached the end of the

 

 

physical memory regions. This is a valid completion case when the size of the physical

 

 

memory regions is larger than the IDE device transfer size.

 

 

 

0

0

Error condition. If the IDE DMA Error bit is 1, there is a problem transferring data to/

 

 

from memory. Specifics of the error have to be determined using bus-specific

 

 

information. If the Error bit is 0, the PRD specified a smaller buffer size than the

 

 

programmed IDE transfer size.

 

 

 

10.6USB Resume Enable Bit

Two bits have been added to the USB Host controller functionality in function 2 of IFB (PCI Register configuration space at Offset C4h). This register is in the resume well of this function.

USB Resume Enable: (IFB Function 2 Config Register)

Address Offset:

C4h

Attribute:

Read/Write

Default Value:

00h

Size:

 

8 bits

 

 

 

Bit

Type

Description

 

 

 

7:2

RO

Reserved

 

 

 

1

RW

PORT1EN: Enable port 1 of the USB controller to look at wakeup events. When set, the

 

 

USB controller will monitor port 1 for remote wakeup and connect/disconnect events.

 

 

When cleared, the USB controller will not look at this port for a wakeup event. For function

 

 

2, this bit applies to port 1.

 

 

 

0

RW

PORT0EN: Enable port 0 of the USB controller to look at wakeup events. When set, the

 

 

USB controller will monitor port 0 for remote wakeup and connect/disconnect events.

 

 

When cleared, the USB controller will not look at this port for a wakeup event. For function

 

 

2, this bit applies to port 0.

 

 

 

For performing legacy power management, the firmware has to set these two bits in each of the functions, if it wants the USB Host controller to monitor these ports.

Intel® 460GX Chipset Software Developer’s Manual

10-19

Page 189
Image 189
Intel 460GX manual USB Resume Enable Bit, Bit Type Description