Intel 460GX 11.2.7ACPI Registers, 11.2.7.1Power Management 1 Status, 11.2.6.2APMS–AdvancedPower Management Status Port (I/O)

LPC/FWH Interface Configuration

11.2.6.2APMS–Advanced Power Management Status Port (I/O)

I/O Address:	0B3h
Default Value:	00h
Attribute:	Read/Write

This register passes status information between the OS and the SMI handler. The IFB operation is not effected by the data in this register.

Bit Description

7:0 APM Status Port (APMS). Writes store data in this register and reads return the last data written.

11.2.7ACPI Registers

The ACPI registers are I/O mapped. The base address is set via PCI Function 0 configuration register 40h. The registers are defined to be compliant with the ACPI 1.0 specification, and use the same bit names. All reserved bits will always return 0 when read, and will have no effect when written.

11.2.7.1Power Management 1 Status

Address Offset:		00-01h
Attributes:		Read/Write
Default Value:		Bit 11:Undefined, All other bits ‘0’
Size:		16 bits
Bit		Description
15	WAK_STS: This bit is set when the system is in one of the Sleep states (via the SLP_EN bit)
	and an enabled IFB wake/break event occurs. Upon setting this bit, IFB will transition the
	system to the ON state. This bit can only be set by hardware and can only be cleared by writing
	a one to this bit position. This bit is not affected by a hard reset caused by a CF9 write.
14:12	Reserved.
11	PWRBTNOR_STS: This bit is set any time a Power Button Override Event occurs. The override
	event occurs when the power button is pressed for 4 consecutive seconds. The power button
	override will cause an unconditional transition to the S5 state, as well as set the AFTERG3 bit.
	The firmware or SCI handler can clear this bit by writing a 1 to it. This bit is not affected by a
	hard reset caused by a CF9 write. Upon reset, this bit is undefined.
10	RTC_STS: This bit is set when the RTC generates an alarm (assertion of the IRQ8# signal).
	Additionally if the RTC_EN bit is set then the setting of the RTC_STS bit will generate wake
	event. This bit is only set by hardware and can only be reset by writing a one to this bit position.
	This bit is not affected by a hard reset caused by a CF9 write.
9	Reserved.
8	PWRBTN_STS: This bit is set by the hardware when the power button is pressed. The firmware
	or SCI handler should clear this bit by writing a 1 to it. This bit is not affected by a hard reset
	caused by a CF9 write.
7:6	Reserved.
5	GBL_STS: This bit is set when an SCI is generated due to the firmware wanting the attention of
	the SCI handler. Firmware has a corresponding bit, BIOS_RLS, which will cause an SCI and set
	this bit. The SCI handler should then clear this bit by writing a 1 to it.
4:1	Reserved.

Intel® 460GX Chipset Software Developer’s Manual 11-31