Intel 460GX Figure 4-3.System I/O Address Space

System Address Map

•I/O addresses used for VGA controllers: 03B0h-03BBh and 03C0h-03DFh. These addresses are specifically decoded so they can be mapped to the PCI bus specified by the VGA Space Register. An I/O access must be contained fully within the VGA I/O range to be remapped (e.g. an I/O read spanning 03BBh and 03BCh would not be remapped because it crosses the VGA I/O range). Posting of this range for writes is controlled by the state of the I/O posting enable bit in the Software-Defined Configuration Register.

•I/O addresses used for the PCI Configuration Space Enable (CSE) protocol. The I/O addresses 0CF8h and 0CFCh are specifically decoded as part of the CSE protocol. These addresses, like the I/O addresses less than 100h, are treated as “defer only” addresses.

•Posting for all other I/O addresses is controlled by the state of the I/O posting enable bit in the Software-Defined Configuration Register. If this bit is set, I/O writes are posted. If this bit is not set, all I/O writes are deferred. I/O reads are always deferred.

Note, the 460GX chipset does not support ISA expansion aliasing. The IFB supports a full I/O space decode, so the compatibility issue will be drivers that rely on the I/O aliasing behavior.

Historically, the 64k I/O space actually was 64k+3 bytes. For the extra 3 bytes, A#[16] is asserted. The 460GX chipset decodes only A#[15:3] when the request encoding indicates an I/O cycle. Therefore accesses with A#[16] asserted are decoded as if they were accesses to address 0 and will be forwarded to the compatibility bus. Since they look like accesses less than 100h, they are always deferred rather than posted. The full address is sent to the PXB and on to the compatibility PCI bus, which therefore has PCI address bit A#[16] active.

At power-on, all I/O accesses are mapped to the compatibility bus. An I/O access is never forwarded inbound by the chipset. The I/O address map is shown in Figure 4-3.

Figure 4-3. System I/O Address Space

1_0003 +3 bytes (Decoded

as 0_000X)

FFFF

Segment 15

F000

4000

	Segment 3
3000
	Segment 2
2000
	Segment 1
1000
	Segment 0
	Compatibility
0000	Bus Only

4-6 Intel® 460GX Chipset Software Developer’s Manual