Data Integrity and Error Handling

(DPE) bit is asserted. Regardless, if the transaction is a read, the PCISTS register’s Parity Error (PE) bit will be set. Additionally, address, command, and data related information is logged in the FEPCIAL and FEPCIL registers if the error is the first error observed by the WXB.

6.12.8.1.6 Other Violations

The PCI specification identifies numerous cases that are violations of the PCI protocol. Other than the cases identified above, the WXB makes no attempt to check for such violations. Response to such violations is undefined. Refer to the PCI specification for a complete description of the required PCI protocol.

6.12.8.2WXB as Target

6.12.8.2.1 Illegal PCI Request Type

The WXB will not claim transactions that use an illegal or unrecognized request type.

6.12.8.2.2 Target Disconnect

The WXB will issue a target disconnect under the following circumstances:

•After the first data transfer if the transaction is using an unrecognized addressing mode (the WXB will only support linear incrementing as a target),

•On reads, when no more data is available in the read buffers, and

These conditions are not treated as an error, and will not be logged or reported.

6.12.8.2.3 Target Retry

The WXB will issue a target retry when:

•A read request is to an address that has already been accepted as a delayed transaction (i.e. the request is already being serviced, but data has not arrived).

•A read request to this address has not yet been accepted by the WXB as a delayed transaction, there is room to enqueue a new delayed transaction, and the request is enqueued.

•A read request is to an address that has not yet been accepted by the WXB and there is no more room to enqueue a new delayed transaction.

•A write request has insufficient buffering in the WXB to allow it to be posted (e.g. a full line is not available for MWI).

•The PCI interface is LOCKED from the host side, unless the transaction is a read request and the data has already been fetched by the WXB.

6.12.8.2.4 Target Abort

The WXB will issue a target abort if a hard fail response is returned over the Expander bus. This response is limited to inbound read requests.

6.12.8.2.5 Other Violations

The PCI specification identifies numerous cases that are violations of the PCI protocol. Other than the cases identified above, the WXB makes no attempt to check for such violations. Response to such violations is undefined. This includes, but is not limited to:

Intel® 460GX Chipset Software Developer’s Manual

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