13.2.4

PCISTS–PCI Device Status Register (Function 2)

13-3

 

13.2.5

RID–Revision Identification Register (Function 2)

13-3

 

13.2.6

CLASSC–Class Code Register (Function 2)

13-4

 

13.2.7

MLT–Master Latency Timer Register (Function 2)

13-4

 

13.2.8

HEDT–Header Type Register (Function 2)

13-4

 

13.2.9

USBBA–USB I/O Space Base Address (Function 2)

13-5

 

13.2.10

SVID–Subsystem Vendor ID (Function 2)

13-5

 

13.2.11

SID–Subsystem ID (Function 2)

13-5

 

13.2.12

INTLN–Interrupt Line Register (Function 2)

13-5

 

13.2.13

INTPN–Interrupt Pin (Function 2)

13-6

 

13.2.14 Miscellaneous Control (Function 2)

13-6

 

13.2.15 SBRNUM–Serial Bus Release Number (Function 2)

13-6

 

13.2.16 LEGSUP–Legacy Support Register (Function 2)

13-6

 

13.2.17 USBREN–USB Resume Enable

13-8

 

13.3 USB Host Controller I/O Space Registers

13-8

 

13.3.1

USBCMD–USB Command Register (I/O)

13-8

 

13.3.2

USBSTS–USB Status Register (I/O)

13-10

 

13.3.3

USBINTR–USB Interrupt Enable Register (I/O)

13-10

 

13.3.4

FRNUM–Frame Number Register (I/O)

13-11

 

13.3.5

FLBASEADD–Frame List Base Address Register (I/O)

13-11

 

13.3.6

SOFMOD–Start of Frame (SOF) Modify Register (I/O)

13-11

 

13.3.7

PORTSC–Port Status and Control Register (I/O)

13-12

14

SM Bus Controller Configuration

14-1

 

14.1 SM Bus Configuration Registers (Function 3)

14-1

 

14.2 System Management Register Descriptions

14-2

 

14.2.1

VID–Vendor Identification Register (Function 3)

14-2

 

14.2.2

DID–Device Identification Register (Function 3)

14-2

 

14.2.3

PCICMD–PCI Command Register (Function 3)

14-2

 

14.2.4

PCISTS–PCI Device Status Register (Function 3)

14-3

 

14.2.5

RID–Revision Identification Register (Function 3)

14-3

 

14.2.6

CLASSC–Class Code Register (Function 3)

14-4

 

14.2.7

SMBBA–SMBus Base Address (Function 3)

14-4

 

14.2.8

SVID–Subsystem Vendor ID (Function 3)

14-4

 

14.2.9

SID–Subsystem ID (Function 3)

14-5

 

14.2.10

INTLN–Interrupt Line Register (Function 3)

14-5

 

14.2.11

INTPN–Interrupt Pin (Function 3)

14-5

 

14.2.12 Host Configuration

14-5

 

14.2.13 smbslvc–SMBus Slave Command (Function 3)

14-6

 

14.2.14 smbshdw1–SMBus Slave Shadow Port 1 (Function 3)

14-6

 

14.2.15 smbshdw2–SMBus Slave Shadow Port 2 (Function 3)

14-6

 

14.3 SMBus I/O Space Registers

14-6

 

14.3.1

smbhststs–SMBus Host Status Register (I/O)

14-7

 

14.3.2

smbslvsts–SMBus Slave Status Register (I/O)

14-7

 

14.3.3

smbhstcnt–SMBus Host Control Register (I/O)

14-8

 

14.3.4

smbhstcmd–SMBus Host Command Register (I/O)

14-9

 

14.3.5

smbhstadd–SMBus Host Address Register (I/O)

14-9

 

14.3.6

smbhstdat0–SMBus Host Data 0 Register (I/O)

14-9

 

14.3.7

smbhstdat1–SMBus Host Data 1 Register (I/O)

14-10

 

14.3.8

smbblkdat–SMBus Block Data Register (I/O)

14-10

 

14.3.9

smbslvcnt–SMBus Slave Control Register (I/O)

14-10

 

14.3.10 smbslvdat–SMBus Slave Data Register (I/O)

14-11

Intel® 460GX Chipset System Software Developer’s Manual

ix

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Intel 460GX manual 13.2.4