Universal Serial Bus (USB)

13

Configuration

The IFB integrates one USB Controller. The USB Controller is UHCI 1.1 compliant and implements the root hub of the USB, which contains two ports.

The IFB PCI Function 2 reflects the USB Host and Root Hubs, with 2 connected USB ports. The register set associated with USB Host Controller is shown below with actual register descriptions given in Section 13.2 and Section 13.3.

13.1PCI Configuration Registers (Function 2)

Table 13-1. PCI Configuration Registers–Function 2

Configuration

Mnemonic

Register

Register

Offset

Access

 

 

 

 

 

 

00–01h

VID

Vendor Identification

RO

 

 

 

 

02–03h

DID

Device Identification

RO

 

 

 

 

04–05h

PCICMD

PCI Command

R/W

 

 

 

 

06–07h

PCISTS

PCI Device Status

R/W

 

 

 

 

08h

RID

Revision Identification

RO

 

 

 

 

09-0Bh

CLASSC

Class Code

RO

 

 

 

 

0Ch

Reserved

 

 

 

 

0Dh

MLT

Latency Timer

R/W

 

 

 

 

0Eh

HEDT

Header Type

RO

 

 

 

 

0F–1Fh

Reserved

 

 

 

 

20–23h

USBBA

USB I/O Space Base Address

R/W

 

 

 

 

24–3Bh

Reserved

 

 

 

 

2C–2Dh

SVID

Subsystem Vendor ID

RO

 

 

 

 

2E–2Fh

SID

Subsystem ID

RO

 

 

 

 

30–3Fh

Reserved

 

 

 

 

3Ch

INTLN

Interrupt Line

R/W

 

 

 

 

3Dh

INTPN

Interrupt Pin

RO

 

 

 

 

3E–5Fh

Reserved

 

 

 

 

60h

SBRNUM

Serial Bus Release Number

RO

 

 

 

 

61–69h

Reserved

 

 

 

 

6A–6Bh

MCR

Miscellaneous Control Register

R/W

 

 

 

 

6C–BFh

Reserved

 

 

 

 

C0–C1h

LEGSUP

Legacy Support

R/W

 

 

 

 

C2-C3h

---

Reserved

---

 

 

 

 

C4h

USBREN

USB Resume Enable

R/W

 

 

 

 

C5-FF

---

Reserved

---

 

 

 

 

Intel® 460GX Chipset Software Developer’s Manual

13-1