Intel 460GX 6.11.4GXB Error Flow, 6.11.3.2Target Retry, 6.11.3.3Target Abort, 6.11.3.5Other Violations, 6.11.3.4Data Parity Errors

Data Integrity and Error Handling

•After the first data transfer if the transaction is using an unrecognized addressing mode (the PXB will only support linear incrementing as a target),

•On reads, when no more data is available in the read buffers, and

•On writes, when the write crosses a 4 KB boundary.

These conditions are not treated as an error, and will not be logged or reported.

6.11.3.2Target Retry

The PXB will issue a target retry when:

•A read request is to an address that has already been accepted as a delayed transaction (i.e. the request is already being serviced, but data has not arrived),

•A write request has insufficient buffering in the PXB to allow it to be posted (a full line is not available for an MWI), or

•The PCI interface is LOCKED from the host side.

6.11.3.3Target Abort

The PXB will issue a target abort if a hard fail response is returned over the Expander bus. This response is limited to inbound read requests.

6.11.3.4Data Parity Errors

When the PXB is a PCI bus target, it will check the data parity provided during write data cycles. For exact details on data errors, see the earlier tables.

6.11.3.5Other Violations

The PCI specification identifies numerous cases that are violations of the PCI protocol. Other than the cases identified above, the PXB makes no attempt to check for such violations. Response to such violations is undefined. This includes, but is not limited to:

•MWI to a misaligned (non-cache-line-boundary) address.

•MWI to an aligned address, but with one or more byte enables not asserted.

Refer to the PCI specification for a complete description of the required PCI protocol.

Note: When multiple errors which cause an SERR# assertion occur within a few cycles of each other, there may not be a separate SERR# assertion for each error.

6.11.4GXB Error Flow

Figure 6-3shows a block diagram of the GXB. On the PCI side, the first error is latched in FERR_PCI. Subsequent errors are latched into NERR_PCI. Errors from PCI will cause the PCI address and data to be latched in PAC_ERR and PD_ERR.

The internal buffers of the GXB are parity protected. Data coming from the graphics card is placed in an inbound buffer with parity generated as for the Expander bus (1 parity bit over 16 bits of data and 2 byte enables). At the top of the inbound queue, the data, BE and parity is sent to the Expander bus as-is out of the queue. There is no checking done in the GXB. If there is bad parity at the SAC, the SAC will flag the error.

6-22 Intel® 460GX Chipset Software Developer’s Manual