Intel 460GX Chipset System Software Developer’s Manual
Intel 460GX Chipset System Software Developer’s Manual
Contents
Coherency
10.1
Latency
10-1
11-8
13.2.4
Figures
Tables
12-11
Introduction
System Overview
Component Overview
Intel 460GX Chipset Components
Name Function
Product Features
Itanium Processor System Bus Support
PXB Features
Dram Interface Support
I/O Support
RAS Features
GXB Features
1 I/O & Firmware Bridge IFB
Other Platform Components
Reference Documents
Programmable Interrupt Device PID
Revision History
Date Description June Initial release
Introduction
Access Mechanism
Register Descriptions
Device Mapping on Bus CBN
Access Restrictions
Partitioning
Device
Reserved Bits Defined in Registers
Default Upon Reset
Register Attributes
Reserved or Undefined Register Locations
Consistency
Configaddress Configuration Address Register
I/O Mapped Registers
Gart Programming Region
1 SAC
Error Handling Registers
Configdata Configuration Data Register
1.1
1.3
Bits Description Disable
1.2
Valid
Ferrsac First Error Status Register
Nerrsac All Error Status Register
Saferr System Address on First Error
Biuitid BIU Itid Register
Biudata BIU Data Register
Address bits
2.2 SEC0ECCFERR ECC on First Memory Card B SEC
2 SDC
2.1 SEC0DFERR Data on First Memory Card B SEC
2.3 SEC0TXINFOFERR Txinfo on First Memory Card B SEC
2.6 DED0TXINFOFERR Txinfo on First Memory Card B DED
2.4 DED0DFERR Data on First Memory Card B DED
2.5 DED0ECCFERR ECC on First Memory Card B DED
2.7 SEC1DFERR Data on First Memory Card a SEC
2.8 SEC1ECCFERR ECC on First Memory Card a SEC
2.9 SEC1TXINFOFERR Txinfo on First Memory Card a SEC
2.10 DED1DFERR Data on First Memory Card a DED
Sdcferr First Error Status Register
2.11 DED1ECCFERR ECC on First Memory Card a DED
2.12 DED1TXINFOFERR Txinfo on First Memory Card a DED
15 ’Forward’ Underflow Card B Right Stack Error FR0
22 ’Forward’ Underflow Card a Right Stack Error FR1
21 ’Forward’ Underflow Card a Left Stack Error FL1
14 ’Forward’ Underflow Card B Left Stack Error FL0
Sdcnerr SDC Next Error Status Register
Pcmdferr Command on First Pcmd Parity Error
Pitidferr Data on First Pitid Parity Error
Sdcrspferr Response on First Sdcrsp Error
Dpbrleferr Private Data Bus Receive Length Error
ECCMSK0 ECC Mask Register Card B
ParMskP PB Parity Mask and IB Correction Enable Register
ECCMSK1 ECC Mask Register Card a
Eccmskf ECC Mask Register
Pvddferr Data on First PVD Parity Error
Pvdparferr Parity on First PVD Parity Error
Pvdtxinfoferr Txinfo on First PVD Parity Error
Secftxinfoferr Txinfo on First System Bus SEC
Secfdferr Data on First System Bus SEC
Secfeccferr ECC on First System Bus SEC
Dedfdferr Data on First System Bus DED
3 MAC
Ferrmac First Error Status Register
Que-Overflow Error
Dedfeccferr ECC on First System Bus DED
Cmndferr Command on First Error
Errsts Error Status Register
4 PXB
Errcmd Error Command Register
5.1
Ferragp First Error Status Register for AGP
5 GXB
Ferrpci
Ferrgart First Error Status Register for Gart
Nerragp Next Errors Status Register for AGP
Pacerr PCI Address & Cmd First Error
Pderr PCI Data First Error
Nerrgart
6 WXB
Nepci Register Records an PCI Bus Error Flag
Fepci Register Records an PCI Bus Error Flag
Bits Description Intrq Asserted Flag
Fepci PCI Bus First Error Status Register
Nepci PCI Bus Next Error Status Register
Performance Monitor Registers
Fepcial PCI First Error Address/Command Log
Fepcidl PCI First Error Data Log
6764 C/BE30 6332 AD6332 310 AD310
Length Encodings
Overflow
Count Value
Dmask Encodings
Umask Encodings
Event Select
Disable Source
Enable Source
Reload Control
2 SDC
FSBDPMD1,0 System Bus Performance Monitor Data Registers
3 PXB
3.1 PMD10 Performance Monitoring Data Register
3.2 PMR10 Performance Monitoring Response
Count Data Cycles
Reload Mode
3.3 PME10 Performance Monitoring Event Selection
Initiating Agent Selection
4 GXB
AGPPMD0,1 AGP Performance Monitor Data Registers
Pcipmd PCI Performance Monitor Data Registers
Percon Performance Monitor Control Register
Event 1 Input
AGPPMC0,1 AGP Performance Monitor Configuration Register
Event 0 Input
Pipe or Sideband Request Mask
Pcipmc PCI Performance Monitor Configuration Register
EVENT1 Count Enable
Initiating Agent
Disable Source
Data Transfer and Transaction Qualifier
PCIWXBPMC0 PCI Performance Monitor Configuration Register
5 WXB
Issuing Agent Qualifier
PCIWXBPMC1 PCI Performance Monitor Configuration Register
Interrupt Related Registers
Xtprs External Task Priority Registers
2.1 I/O Register Select Register FEC00000h
Address Name Access Default Value
PID PCI Memory-mapped Registers
Memory-Mapped Register Summary
XAPIC EOI Register FEC00040h
PID Indirect Access Registers
2.2 I/O Window Register FEC00010h
I/O Window Register Format
Offset Name Access Default Value
3.1 I/O xAPIC ID Register 00h
RTE
Memory-mapped Register Summary Cont’d
I/O Apic ID Register Format
3.2 I/O xAPIC Version Register 01h
3.3 I/O xAPIC Arbitration ID Register 02h
I/O xAPIC Version Register Format
I/O xAPIC Arbitration ID Register Format
Bits Sapic Mode Apic Mode Description Name
3.4 I/O xAPIC RTE 10h-8Fh
10. I/O xAPIC RTE Format
Sapic Mode Apic Mode Description Name
10. I/O xAPIC RTE Format Cont’d
Destination
Vector
System Architecture
Coherency
Processor Coherency
Ordering
PCI Coherency
AGP Coherency
WXB Arbitration
WXB Arbitration at the PCI Bus
Arbitration for Inbound Transactions
Processor Locks
Big-endian Support
Indivisible Operations
Arbitration for Outbound Transactions
Atomic Reads
Inbound PCI Locks
Atomic Writes
Locks with AGP Non-coherent Traffic
Interrupt Delivery
WXB PCI Hot-Plug Support
Slot Power-up and Enable
Slot Power-down and Disable
System Architecture
System Address Map
Memory Map
Compatibility Region
System Firmware
System Memory Address Space
Low Extended Memory Region
Medium Extended Memory Region
High Extended Memory above 4G
Re-mapped Memory Areas
Variable GAP
I/O Address Map
Itanium Processor and Chipset-specific Memory Space
System I/O Address Space
Devices View of the System Memory Map
High PXB must ignore GXB must BINIT# after Gart
Legal and Illegal Address Disposition
Address Disposition
Address Range Outbound Inbound Dest. Decision
Above TOM
Address Disposition Cont’d
Main memory if present above 4 GB
Binit
System Address Map
Organization
General Memory Characteristics
Memory Subsystem
System
Maximum Memory Configuration Using Two Cards
Dimm Types
Minimum/Maximum Memory Size per Configuration
Technology & Configuration Size
Double Number Memory Size
Interleaving/Configurations
Address Interleaving
Summary of Configuration Rules
Non-uniform Memory Configurations
Bandwidth
Auto Detection
Supporting Features
Memory Subsystem Clocking
Removing a Bad Row
Scrubbing Time
Hardware Initialization
Memory Scrubbing
Memory Size Time to Scrub
Memory Subsystem
Data Integrity and Error Handling
Integrity
System Bus
PCI Buses
Dram
Expander Buses
5 AGP
Usage of First-error and Next-error
Memory ECC Routing
Data Poisoning
Masked Bits
BERR#/BINIT# Generation
INTREQ#
XBINIT#
SAC/SDC Errors
Data ECC or Parity Errors
XSERR#
System Bus Errors
SAC to SDC Interface Errors
SAC to MAC Interface Errors
5 SDC/Memory Card Interface Errors
Error Determination
6 SDC/System Bus Errors
SDC Internal Errors
SAC Address on an Error
SDC Logging Registers
Special Notes on Usage of SECTID, DEDTID, Fsetid Registers
Clearing Errors
Multiple Errors
1 SAC/SDC Error Clearing
SDC Multiple Errors
ERR ERR
SAC Multiple Errors
Single Errors with Multiple Reporting
Error Anomalies
Data Flow Errors
SAC Error Flow on Data
Error Conditions
Table of Errors
Error Cases
SAC to SDC Interface Errors
System Bus ADD/CMND
Error Cases Cont’d
Internal SDC Error
PXB Errors
Detected as PCI Master
PXB as Master
PCI Integrity
PCI Bus Monitoring
Master Abort
PXB as Target
GXB Error Flow
Target Retry
Target Abort
GXB Error Signals
GXB Errors
Gart Interface Errors
Multiple Errors
GXB Error Flow
Integrity
WXB Data Integrity and Error Handling
Usage of First Error and Next Error Registers
Data Parity Poisoning
Supported Error Escalation to XBINIT#a
Error Mask Bits
Error Steering/Signaling
Abbreviation Error
SERR# Generation
Supported Error Escalation to SERROUT#a
Supported Error Escalation to PA/BINTRQ#
Escalation
Error Determination and Logging
INTRQ# Interrupt
XBINIT# Generation
Error Conditions
WXB as Bus Master
WXB as Target
Other Violations
PCI Interface Errors
System Error Signaled
Discard Timer Expiration
AGP Subsystem
Graphics Address Relocation Table Gart
22b
12b
24b
14b
Gart Implementation
Gart Entry Format for 4kB Pages
Gtlb
Programming Gart
Sizes
Parity
Coherency
SGW#
SE2 ADSC# ADSP# ADV# LBO# SB# SW#
Interrupt Handling
4.1 3.3V AGP 1X and 2X Mode Compatibility
AGP Traffic
Addresses Used by the Graphics Card
Traffic Priority
Coherency, Translation and Types of AGP Traffic
Ordering Rules
Processor Locks and AGP Traffic
Coherency for AGP/PCI Streams
PCI Semantics Traffic
Address Faults
Address Alignment and Transfer Sizes
Inbound Reads
Inbound Delayed Read Matching Rules
PCI Stream Read Prefetching
Inbound Reads Directed To Memory
Inbound I/O Reads
Delayed Read Matching Criteria
Command Address BEs
Inbound Writes
Retry/Disconnect Conditions
Outbound Reads
Outbound Writes
Burst Write Combining Modes
Transfer Data Length Combining Supported Used Mode
Fast Back-to-Back Transactions
1st write 2nd write 3rd write Transferred as
Inbound Read Prefetching
Latency
GXB Address Map
Bandwidth Estimates for Various Request Sizes
AGP Subsystem
AGP Subsystem
Ihpc Configuration Registers
WXB Hot-Plug
Ihpc Configuration Register Space
Number List for the Ihpc PCI Register Descriptions
VID Vendor Identification Register
Did Device Identification Register
Pcicmd PCI Command Register
Pcists PCI Status Register
RID Revision Identification Register
CLS Cache Line Size
MLT Master Latency Timer Register
Class Class Register
HDR Header Register
SID Subsystem ID
Base Address
Svid Subsystem Vendor Identification
Interrupt Line
Miscellaneous Hot-Plug Configuration
Interrupt Pin
Hot-Plug Slot Identifier
Hot-Plug Features
Switch Change Serr Status
Power Fault Serr Status
Ihpc Memory Mapped Registers
Memory Access Index
Memory Mapped Register Access Port
Arbiter Serr Status
Ihpc Memor Mapped Register Space
M66EN
Slot Enable
Number List for Ihpc Memory Mapped Register Descriptions
Hot-Plug Miscellaneous
LED Control
Hot-Plug Interrupt Input and Clear
Hot-Plug Interrupt Mask
Serial Input Byte Data
Serial Input Byte Pointer
General Purpose Output
Hot-Plug Non-interrupt Inputs
Hot-Plug Switch Interrupt Redirect Enable
Slot Power Control
Extended Hot-Plug Miscellaneous
Mnemonic Register Register Access
PCI / LPC / FWH Configuration
PCI Configuration Registers Function
IFB Register Mapping
Classc
Biosen
Pcists
Hedt
IDE Configuration
PCI Configuration Registers-Function 1 IDE Interface
Universal Serial Bus USB Configuration
PCI Configuration Registers-Function 2 USB Interface
Configuration Offset Mnemonic Register
SMBus Controller Configuration
SMBus Configuration Registers Function
IFB Register Mapping
CD-ROM Auto RUN Feature of the OS
Usage of 1MIN Timer in Power Management
Usage of the SW SMI# Timer
IFB Usage Considerations
Disabled Enabled
Ultra DMA Configuration
Reserved Secondary Primary Drive Ultra DMA Mode Enable
SSDE1 SSDE0 PSDE1 PSDE0
Capability Word Bits Field Offset
Determining a Drive’s Transfer Rate Capabilities
Overview
Ultra DMA Fields that Indicate Ultra DMA Drive Capabilities
Capability Word Bits
DMA
PIO
Determining a Drive’s Best Ultra DMA Capability
Capability Word Bits Field
Capability Word Offset Bits Field
150 Minimum Multi Word DMA Transfer Cycle Time per
10-6
Drives Reported DMA Drive’s Best DMA Mode Cycle Time
Determining a Drive’s Best PIO Capability
Drives Reported PIO Drive’s Best PIO Mode
Drive PIO Capability as a Function of Cycle Time
IFB Drive Mode Based on DMA/PIO Capabilities
IFB Timing Settings
10.5.6.1 DMA/PIO Timing Settings
Mode Yes Disabled Enabled DMA Mode Iordy If fixed disk
DMA Iordy IDE
10. Ultra DMA Timing Value Based on Drive Mode
Drive Configuration for Selected Timings
Ultra DMA Timing Settings
DMA/PIO Timing Values Based on Piix Cable Mode/System Speed
12. PIO Transfer/Mode Values
Drive’s Selected PIO Speed Capability
10-12
Settings Checklist
13. Drive Capabilities Checklist
14. IFB Settings Checklist
Example Configurations
Example #1 Ultra DMA/33 Configuration
Register Type Offset Value Comments
4A-4Bh 0002h Ultra DMA mode config
Example #3 Non Ultra DMA/33 Drive Configuration
40-41h E377h Mode config. for Primary IDE Timing Register
44h 0Bh Ultra DMA Control Register
Ultra DMA System Software Considerations
4A-4Bh 0000h
10-16
Intel 460GX Chipset Software Developer’s Manual 10-17
Bit Description
Bit Description Reserved. This bit is hardwired to
BMISX-Bus Master IDE Status Register I/O
Completed or halted
USB Resume Enable Bit
Bit Type Description
10-20
LPC/FWH Interface Configuration
VID-Vendor Identification Register Function
DID-Device Identification Register Function
PCICMD-PCI Command Register Function
PCISTS-PCI Device Status Register Function
HEDT-Header Type Register Function
RID-Revision Identification Register Function
CLASSC-Class Code Register Function
Bit
Acpi Enable Function
Acpi Base Address Function
SCI IRQ Routing Control
BIOSEN-BIOS Enable Register Function
PIRQRCAD-PIRQx Route Control Registers Function
SerIRQC-Serial IRQ Control Register Function
TOM-Top of Memory Register Function
MSTAT-Miscellaneous Status Register Function
Deterministic Latency Control Register Function
PDMACFG-PCI DMA Configuration Resister Function O
MGPIOC-Muxed Gpio Control Function
Bits Description
RTCCFG-Real Time Clock Configuration Register Function
Base Offset Channel
LPC COM Decode Ranges Function
Gpio Enable Function
Gpio Base Address Function
Bits Decode Range
011
LPC FDD/LPT Decode Ranges Function
000
110
220 233 240 253 260 273 280 293
LPC Sound Decode Ranges Function
LPC Generic Decode Range Function
11-12
Reserved. This bit must be a
LPC Enables Function
Firmware Hub FWH Decode Enable Register
1413 Reserved
Firmware Hub FWH Select Register
PCI to LPC I/O Space Registers
Test Mode Register
Dcom-Dma Command Register I/O
DMA Registers
Dcm-Dma Channel Mode Register I/O
Dr-Dma Request Register I/O
WSMB-Write Single Mask Bit I/O
RWAMB-Read / Write All Mask Bits I/O
Bit Description Reserved. Must be
Ds-Dma Status Register I/O
DBADDR-DMA Base and Current Address Registers I/O
DLPAGE-DMA Low Page Registers I/O
When counting down a DMA transfer
DBCNT-Dma Base and Current Count Registers I/O
DCBP-Dma Clear Byte Pointer Register I/O
Dmc-Dma Master Clear Register I/O
11.2.2.1 Icw1-Initialization Command Word 1 Register I/O
Interrupt Controller Registers
Dclm-Dma Clear Mask Register I/O
11.2.2.2 Icw2-Initialization Command Word 2 Register I/O
11.2.2.3 Icw3-Initialization Command Word 3 Register I/O
Bit Description Reserved. Must be programmed to all 0s
11.2.2.6 Ocw1-Operational Control Word 1 Register I/O
11.2.2.4 Icw3-Initialization Command Word 3 Register I/O
11.2.2.5 Icw4-Initialization Command Word 4 Register I/O
11-22
11.2.2.7 Ocw2-Operational Control Word 2 Register I/O
11.2.2.8 Ocw3-Operational Control Word 3 Register I/O
Elcr1-Edge/Level Control Register I/O
Elcr2-Edge/Level Control Register I/O
Counter/Timer Registers
Tcw-Timer Control Word Register I/O
Bit Decription
5. When bit 2=0, status and/or count will not be latched
Latched. When bit 4=1, the status will not be latched
5. When bit 3=0, status and/or count will not be latched
5. When bit 1=0, status and/or count will not be latched
TMRSTS-Timer Status Registers I/O
TMRCNT-Timer Count Registers I/O
NMI Registers
Nmisc-Nmi Status and Control Register I/O
RTCD-Real-time Clock Data Register I/O
NMI Enable. Used by IFB NMI logic
Real Time Clock Registers
Used for NMI enabling/disabling. See description in Section
RTCEI-Real-time Clock Extended Index Register I/O
Advanced Power Management APM Registers
APMC-Advanced Power Management Control Port I/O
RTCED-Real-time Clock Extended Data Register I/O
APMS-Advanced Power Management Status Port I/O
Power Management 1 Status
Acpi Registers
States can be supported in external logic
Power Management 1 Enable
Power Management 1 Control
11-32
General Purpose 0 Status
Power Management 1 Timer
Bit Description Bits Mode
3124 Reserved 230
1512 Reserved
General Purpose 0 Enable
Power up, this bit is set to ‘1’
CF9 write
General Purpose 1 Enable
SMI Registers
General Purpose 1 Status
Status Register is set
Global Control and Enable
Port at B2h in I/O space
Thrmsts bit
GPIO8
General Purpose I/O Registers
Global Status Register
GPIO7
GP Output
GP Data
159 Reserved
GP TTL
1916
Bit is set
GP Blink
GP Lock
GP Invert
GP Core
GP SMI
GP Pulse
GP Pull-up
11-42
Configuration Mnemonic Register
IDE Configuration
PCI Configuration Registers Function
IDE Controller Register Descriptions PCI Function
Parity Error Response. This bit is hardwired to
SERR# Enable. This bit is hardwired to
Wait Cycle Control. This bit is hardwired to
VGA Palette Snoop. This bit is hardwired to
SERR# Status. Read as
By writing a 1 to this bit
MLT-Master Latency Timer Register Function
BMIBA-Bus Master Interface Base Address Register Function
Bus Master interface registers and correspond to AD154
SVID-Subsystem Vendor ID Function
SID-Subsystem ID Function
IDETIM-IDE Timing Register Function
SIDETIM-Slave IDE Timing Register Function
DMACTL-Synchronous DMA Control Register Function
Bit Description Reserved
SDMATIM-Synchronous DMA Timing Register Function
IDE Controller I/O Space Registers
BMICx-Bus Master IDE Command Register I/O
Ultra DMA/33 Timing Mode Settings
Ultra DMA/33 Timing Modes
BMISx-Bus Master IDE Status Register I/O
Interrupt/Activity Status Combinations
Is equal to the IDE device transfer size
312
12-12
Universal Serial Bus USB Configuration
PCI Configuration Registers-Function
Usbren
USB Host Controller Register Descriptions PCI Function
Bit Description 1510 Reserved. Read
Reserved. Read as
Resets STA to 0 by writing a 1 to this bit
Reserved. Read as 0’s
This field
Register in Function
13-4
USBBA-USB I/O Space Base Address Function
INTLN-Interrupt Line Register Function
SBRNUM-Serial Bus Release Number Function
INTPN-Interrupt Pin Function
Miscellaneous Control Function
LEGSUP-Legacy Support Register Function
Appropriate enable bits are set
Default to 1 for compatibility with older USB software
Needs to be serviced later
Accesses that are part of the sequence
USBREN-USB Resume Enable
USBCMD-USB Command Register I/O
USB Host Controller I/O Space Registers
Stop=0, the Frnum register can be reprogrammed
Run/Stop, Debug Bit Interaction
Swdbg Bit Run/Stop Bit Operation
By Software or Hardware
Interrupt is generated to the system
USBINTR-USB Interrupt Enable Register I/O
USBSTS-USB Status Register I/O
Register =
FLBASEADD-Frame List Base Address Register I/O
Address signals
FRNUM-Frame Number Register I/O
SOFMOD-Start of Frame SOF Modify Register I/O
PORTSC-Port Status and Control Register I/O
EOF2 time See of the USB Specification
X0 Disable
Asserted, the corresponding port is disabled
Register define the hub states as follows
13-14
Class Code 0C-1Fh Reserved
SM Bus Controller Configuration
SM Bus Configuration Registers Function
Base Address Register
System Management Register Descriptions
Shutdown special cycle
14-2
STA to 0 by writing a 1 to this bit
SMBBA-SMBus Base Address Function
14-4
Host Configuration
Interrupt pin PIRQB# is used
Smbshdw1-SMBus Slave Shadow Port 1 Function
Smbslvc-SMBus Slave Command Function
SMBus I/O Space Registers
Smbshdw2-SMBus Slave Shadow Port 2 Function
Smbslvsts-SMBus Slave Status Register I/O
Transaction errors are caused by
Smbhststs-SMBus Host Status Register I/O
Position
Smbhstcnt-SMBus Host Control Register I/O
Smbhstadd-SMBus Host Address Register I/O
Smbhstcmd-SMBus Host Command Register I/O
Command field of SMBus host transaction
Smbhstdat0-SMBus Host Data 0 Register I/O
Smbhstdat1-SMBus Host Data 1 Register I/O
Smbblkdat-SMBus Block Data Register I/O
Smbslvcnt-SMBus Slave Control Register I/O
14.3.9.2 10.3.11.smbslvevt-SMBus Slave Event Register I/O
14.3.9.1 Smbshdwcmd -SMBus Shadow Command Register I/O
Smbslvdat-SMBus Slave Data Register I/O
Address 10h or one of the slave shadow port addresses
14-12
PCI/LPC Bridge Description
PCI Interface
Interrupt Controller
Initialization Command Words ICWs
Programming the Interrupt Controller
15-2
End of Interrupt Operation
Operation Command Words OCWs
Automatic End of Interrupt Aeoi Mode
End of Interrupt EOI
Modes of Operation
Fully Nested Mode
Special Fully Nested Mode
Automatic Rotation Equal Priority Devices
Cascade Mode
Poll Command
Specific Rotation Specific Priority
Interrupt Masks
Edge and Level Triggered Mode
Special Mask Mode
Masking on an Individual Interrupt Request Basis
Reading the Interrupt Controller Status
Interrupt Steering
Serial Interrupts
Quiet Active Mode
Continuous Idle Mode
Protocol
Data Frame Number Usage # Clocks Past Start
Stop Frame
Serirq Frames
3222
Timer/Counters
Programming the Interval Timer
15-10
Interval Timer Control Word Format
Write Operations
Counter I/O Port Read
Counter Latch Command
Read Operations
15-12
Read Back Command
Real Time Clock
RTC Registers and RAM
RTC Standard RAM Bank
Index Address Name
15.5.1.1 Register a
1 Invalid 0 Invalid
90625 ms 8125 ms
15.5.1.2 Register B
15.5.1.3 Register C
RSMRST#
Lockable RAM Ranges
RTC Update Cycle
RTC Interrupts
15.5.1.4 Register D
15-18
Overview
IFB Power Management
IFB Power States and Consumption
Acpi State Description
16.2.2 SMI# Generation
IFB Power Planes
Power Plane Descriptions
Causes of SMI#
Causes of SCI#
SCI Generation
Sleep States
SCI Event Comment
Acpi Bits Not Implemented in IFB
Acpi Bits Not Implemented by IFB
Entry/Exit for the S4 and S5 States
Offset Register Name/Function Comment
Handling of Power Failures in IFB
Action after Power Returns
S5 Wake Event Comment
16-6