Register Descriptions

Table 2-10. I/O (x)APIC RTE Format (Cont’d)

Register Offset: 10-8Fh

Default Value: Undefined except mask bit is 1Attribute: Read/Write

 

 

 

 

Bit(s)

SAPIC Mode

APIC Mode

Description

Name

Name

 

 

 

 

 

 

16

MASK

MASK

This bit masks the (x)APIC delivery of this interrupt.

 

 

 

A 0 indicates that delivery of this interrupt is not masked. An edge or level on

 

 

 

an interrupt pin that is not masked results in the delivery of the interrupt to the

 

 

 

destination.

 

 

 

A 1 indicates that delivery of this interrupt is masked. It is the software’s

 

 

 

responsibility to deal with the case where the mask bit is set after the interrupt

 

 

 

message has been accepted by a local (x)APIC unit but before the interrupt is

 

 

 

dispensed to the processor.

 

 

 

When the mask bit is 1, interrupts coming into the PID are routed to the INTIO,

 

 

 

I2O_INT#, or I2B pins, provided they are correctly mapped. No delivery status

 

 

 

bit latching is performed in this mode.

 

 

 

When the mask bit is a 0, interrupts are latched in the delivery status bit. If the

 

 

 

mask bit is set to a 1 after the interrupt is latched but before it is delivered, the

 

 

 

latched value will be held until the interrupt is unmasked and delivered.

 

 

 

 

15

TRIGGER

TRIGGER

The trigger mode field indicates the type of signal on the interrupt pin that

 

MODE

MODE

triggers an interrupt.

 

 

 

A 0 indicates edge sensitive.

 

 

 

A 1 indicates level sensitive.

 

 

 

 

14

RIRR

RIRR

This bit is read-only. During (x)APIC mode, this bit is used for level-triggered

 

 

 

interrupts. Its meaning is undefined for edge-triggered interrupts. For level-

 

 

 

triggered interrupts, this bit is set when the local (x)APIC(s) accepts the level

 

 

 

interrupt sent by the PID. The RIRR bit is reset when an EOI message is

 

 

 

received from the local (x)APIC.

 

 

 

 

13

POLARITY

POLARITY

This bit specifies the polarity of each interrupt signal connected to the interrupt

 

 

 

pins of the PID. A value of 0 means the signal is high-active and a value of 1

 

 

 

means the signal is low-active. In the case of level, high-active means if the pin

 

 

 

is sampled high, it is considered active. In the case of an edge, high-active

 

 

 

means the low-to-high edge is considered active.

 

 

 

 

12

DELIVERY

DELIVERY

This bit is read-only. It holds the current status of interrupt delivery to the

 

STATUS

STATUS

processor. This bit functions differently depending on the Trigger Mode bit.

 

 

 

When the Trigger Mode bit indicates edge sensitive:

 

 

 

The Delivery Status bit is set when an active edge is detected on the interrupt

 

 

 

pin.

 

 

 

The Delivery Status bit is reset when the interrupt message is successfully sent

 

 

 

to the processor.

 

 

 

When the Trigger Mode bit indicates level sensitive:

 

 

 

The Delivery Status bit reflects the assertion of the pin. i.e. If the pin is at its

 

 

 

active level, according to its Polarity bit, the Delivery Status bit is set; If the pin

 

 

 

is at its inactive level, according to its Polarity bit, the Delivery status bit is

 

 

 

reset.

 

 

 

To accurately determine the delivery status of an interrupt in level mode the

 

 

 

RIRR bit must be considered as well as the Delivery Status bit.

 

 

 

 

Intel® 460GX Chipset Software Developer’s Manual

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