Intel 460GX manual PCI to LPC I/O Space Registers, DMA Registers, Test Mode Register

LPC/FWH Interface Configuration

Bit	Description
7:4	FWH_C8_IDSEL: This dictates the IDSEL of 512 KB of the FWH memory range starting at 4 GB -
	3.5 MB (FFC80000H) to 4 GB - 3 MB (FFCFFFFFH) as well as register space starting at (4 GB-
	4MB) - 3.5MB (FF880000h) to (4 GB-4MB) - 3MB (FF8FFFFFh). The enable for this range is
	controlled through bit 1 of the FWH Decode Enable Register at E3H.
3:0	FWH_C0_IDSEL: This dictates the IDSEL of 512 KB of the FWH memory range starting at 4 GB -
	4 MB (FFC00000H) to 4 GB - 3.5 MB (FFC7FFFFH) as well as register space starting at (4 GB-
	4MB) – 4MB (FF800000h) to (4 GB-4MB) - 3.5MB (FF87FFFFh). The enable for this range is
	controlled through bit 0 of the FWH Decode Enable Register at E3H.

11.1.27.3Test Mode Register

Address:FC-FFh

Default Value:00000000h

Attributes:Read/Write

Bit	Description
31:1	Reserved.

0Alternate Access Mode Enable: When set, the part enters alternate access mode. This allows reads to certain write-only registers and writes to certain read-only registers. Read to Port 70h will return the NMI mask value. See Section 10.3 of the RS-IFB (I/O & Firmware Bridge) External Design Specification, Rev 2.0, for more detail.

11.2PCI to LPC I/O Space Registers

11.2.1DMA Registers

The IFB contains DMA circuitry that incorporates the functionality of two 82C37 DMA controllers (DMA1 and DMA2). The DMA registers control the operation of the DMA controllers and are all accessible from the Host CPU via the PCI Bus interface.

11.2.1.1Dcom–Dma Command Register (I/O)

I/O Address:	Channels 0-3–08h; Channels 4-7–0D0h
Default Value:	00h (CPURST or Master Clear)
Attribute:	Write Only

This 8-bit register controls the configuration of the DMA. Note that disabling channels 4-7 also disables channels 0-3, since channels 0-3 are cascaded onto Channel 4.

Bit	Description
7	Reserved. Must be 0.
6	Reserved. Must be 0.
5	Reserved. Must be 0.
4	DMA Group Arbitration Priority. 1=Rotating priority; 0=Fixed priority
3	Reserved. Must be 0
2	DMA Channel Group Enable. 1=Disable; 0 = Enable.
1:0	Reserved. Must be 0.

Intel® 460GX Chipset Software Developer’s Manual 11-15