8.2.14

Extended Hot-Plug Miscellaneous

8-18

9

IFB Register Mapping

9-1

 

9.1

PCI / LPC / FWH Configuration

9-1

 

 

9.1.1

PCI Configuration Registers (Function 0)

9-1

 

9.2

IDE Configuration

9-3

 

 

9.2.1

PCI Configuration Registers (Function 1)

9-3

 

9.3

Universal Serial Bus (USB) Configuration

9-4

 

 

9.3.1

PCI Configuration Registers (Function 2)

9-4

 

9.4

SMBus Controller Configuration

9-5

 

 

9.4.1

SMBus Configuration Registers (Function 3)

9-5

10

IFB Usage Considerations

10-1

 

10.1

Usage of 1MIN Timer in Power Management

10-1

 

10.2

Usage of the SW SMI# Timer

10-1

 

10.3

CD-ROM AUTO RUN Feature of the OS

10-1

 

10.4

ACPI, SMBus, GPIO Base Address Reporting to the OS

10-1

 

10.5

Ultra DMA Configuration

10-2

 

 

10.5.1

UDMAC–Ultra DMA Control Register (IFB Function 1 PCI

 

 

 

 

Configuration Offset 48h)

10-2

 

 

10.5.2

UDMATIM–Ultra DMA Timing Register (IFB Function 1 PCI

 

 

 

 

Configuration Offsets 4A-4Bh)

10-2

 

 

10.5.3

Determining a Drive’s Transfer Rate Capabilities

10-3

 

 

10.5.4

Determining a Drive’s Best Ultra DMA Capability

10-5

 

 

10.5.5

Determining a Drive’s Best Multi Word DMA/Single Word DMA

 

 

 

 

(Non-ultra DMA) Capability

10-5

 

 

10.5.6

IFB Timing Settings

10-9

 

 

10.5.7

Drive Configuration for Selected Timings

10-11

 

 

10.5.8

Settings Checklist

10-13

 

 

10.5.9

Example Configurations

10-14

 

 

10.5.10

Ultra DMA System Software Considerations

10-16

 

 

10.5.11 Additional Ultra DMA/PCI Bus Master IDE Device Driver

 

 

 

 

Considerations

10-17

 

10.6

USB Resume Enable Bit

10-19

11

LPC/FWH Interface Configuration

11-1

 

11.1

PCI to LPC/FWH Interface Configuration Space Registers (PCI Function 0) ..

11-1

 

 

11.1.1

VID–Vendor Identification Register (Function 0)

11-1

 

 

11.1.2

DID–Device Identification Register (Function 0)

11-1

 

 

11.1.3

PCICMD–PCI Command Register (Function 0)

11-2

 

 

11.1.4

PCISTS–PCI Device Status Register (Function 0)

11-2

 

 

11.1.5

RID–Revision Identification Register (Function 0)

11-3

 

 

11.1.6

CLASSC–Class Code Register (Function 0)

11-3

 

 

11.1.7

HEDT–Header Type Register (Function 0)

11-3

 

 

11.1.8

ACPI Base Address (Function 0)

11-4

 

 

11.1.9

ACPI Enable (Function 0)

11-4

 

 

11.1.10

SCI IRQ Routing Control

11-4

 

 

11.1.11

BIOSEN–BIOS Enable Register (Function 0)

11-5

 

 

11.1.12

PIRQRC[A:D]–PIRQx Route Control Registers (Function 0)

11-5

 

 

11.1.13

SerIRQC–Serial IRQ Control Register (Function 0)

11-6

 

 

11.1.14

TOM–Top of Memory Register (Function 0)

11-6

 

 

11.1.15

MSTAT–Miscellaneous Status Register (Function 0)

11-7

Intel® 460GX Chipset System Software Developer’s Manual

vii

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Intel 460GX manual 10-1