2.11 DED1ECCFERR ECC on First Memory Card a DED | Intel 460GX

Register Descriptions

2.4.2.11DED1_ECC_FERR: ECC on First Memory Card A DED

Bus CBN, Device Number:	04h
Address Offset:	78h	Size:	8 bits
Default Value:	00h	Attribute:	Read Only, New Value Latched
			anytime appropriate FERR register
			bit is set

This register records and latches the ECC checkbits corresponding to the first DED detected by memory interface 0 in the SDC.

Bits Description

7:0 ECC - ECC of Error.

2.4.2.12DED1_TXINFO_FERR: TXINFO on First Memory Card A DED

Bus CBN, Device Number:	04h
Address Offset:	79-7Ah	Size:	16 bits
Default Value:	00h	Attribute:	Read Only, New Value Latched
			anytime appropriate FERR register
			bit is set

This register records the ITID and failing chunk corresponding to the first DED detected by memory interface 1 in the SDC.

Bits Description

15:9 reserved(0)

8:6 DC - Data Chunk of ITID.

5:0 ITID - ITID of error.

2.4.2.13SDC_FERR: First Error Status Register

Bus CBN, Device Number: 04h
Address Offset:	80-83h	Size:	32 bits
Default Value:	0000h	Attribute:	Read/Write to Clear

This register records the first error condition detected in the SDC. Writing a ’1’ to this register will clear the bit in both SDC_FERR and the same bit in SDC_NERR.

Bits Description

31Simultaneous S/W write-one-to-clear and H/W error detected in the same cycle. This bit will only be set if another bit is also set. This implies that the ERROR>_<TYPE>_FERR data registers associated with the other asserted bit contain stale data.

30PDB Receive Length Error (RLE) Private Bus receive length error

29DRDY# Protocol Error (FS2)

Asserted when a protocol error is found involving DRDY#, SBUSY# and DBUSY#.

28Write Data Protocol Error (FS1) Asserted on write protocol errors.

27LEN# Protocol Error (FS0)

Asserted on mismatches of LEN# field and actual data transmitted.

2-14	Intel® 460GX Chipset Software Developer’s Manual

Image 34

Intel 460GX manual 2.11 DED1ECCFERR ECC on First Memory Card a DED, 2.12 DED1TXINFOFERR Txinfo on First Memory Card a DED

Contents

Intel 460GX Chipset System Software Developer’s Manual Intel 460GX Chipset System Software Developer’s Manual Contents Coherency 10.1 Latency 10-1 11-8 13.2.4 Figures Tables 12-11 Introduction System Overview Intel 460GX Chipset Components Component OverviewName Function Product Features Itanium Processor System Bus Support Dram Interface Support PXB FeaturesI/O Support RAS Features GXB Features 1 I/O & Firmware Bridge IFB Other Platform ComponentsReference Documents Programmable Interrupt Device PID Revision History Date Description June Initial release Introduction Access Mechanism Register Descriptions Device Mapping on Bus CBN Access RestrictionsPartitioning Device Reserved Bits Defined in Registers Default Upon ResetRegister Attributes Reserved or Undefined Register Locations Consistency Configaddress Configuration Address RegisterI/O Mapped Registers Gart Programming Region 1 SAC Error Handling RegistersConfigdata Configuration Data Register 1.1 1.3 Bits Description Disable1.2 Valid Ferrsac First Error Status Register Nerrsac All Error Status Register Saferr System Address on First Error Biuitid BIU Itid Register Biudata BIU Data Register Address bits 2.2 SEC0ECCFERR ECC on First Memory Card B SEC 2 SDC2.1 SEC0DFERR Data on First Memory Card B SEC 2.3 SEC0TXINFOFERR Txinfo on First Memory Card B SEC 2.6 DED0TXINFOFERR Txinfo on First Memory Card B DED 2.4 DED0DFERR Data on First Memory Card B DED2.5 DED0ECCFERR ECC on First Memory Card B DED 2.7 SEC1DFERR Data on First Memory Card a SEC 2.9 SEC1TXINFOFERR Txinfo on First Memory Card a SEC 2.8 SEC1ECCFERR ECC on First Memory Card a SEC2.10 DED1DFERR Data on First Memory Card a DED 2.11 DED1ECCFERR ECC on First Memory Card a DED Sdcferr First Error Status Register2.12 DED1TXINFOFERR Txinfo on First Memory Card a DED 15 ’Forward’ Underflow Card B Right Stack Error FR0 22 ’Forward’ Underflow Card a Right Stack Error FR121 ’Forward’ Underflow Card a Left Stack Error FL1 14 ’Forward’ Underflow Card B Left Stack Error FL0 Pcmdferr Command on First Pcmd Parity Error Sdcnerr SDC Next Error Status RegisterPitidferr Data on First Pitid Parity Error Dpbrleferr Private Data Bus Receive Length Error Sdcrspferr Response on First Sdcrsp ErrorECCMSK0 ECC Mask Register Card B ECCMSK1 ECC Mask Register Card a ParMskP PB Parity Mask and IB Correction Enable RegisterEccmskf ECC Mask Register Pvdparferr Parity on First PVD Parity Error Pvddferr Data on First PVD Parity ErrorPvdtxinfoferr Txinfo on First PVD Parity Error Secftxinfoferr Txinfo on First System Bus SEC Secfdferr Data on First System Bus SECSecfeccferr ECC on First System Bus SEC Dedfdferr Data on First System Bus DED 3 MAC Ferrmac First Error Status RegisterQue-Overflow Error Dedfeccferr ECC on First System Bus DED Errsts Error Status Register Cmndferr Command on First Error4 PXB Errcmd Error Command Register 5.1 Ferragp First Error Status Register for AGP5 GXB Ferrpci Ferrgart First Error Status Register for Gart Nerragp Next Errors Status Register for AGP Pderr PCI Data First Error Pacerr PCI Address & Cmd First ErrorNerrgart 6 WXB Nepci Register Records an PCI Bus Error FlagFepci Register Records an PCI Bus Error Flag Bits Description Intrq Asserted Flag Fepci PCI Bus First Error Status Register Nepci PCI Bus Next Error Status Register Performance Monitor Registers Fepcial PCI First Error Address/Command LogFepcidl PCI First Error Data Log 6764 C/BE30 6332 AD6332 310 AD310 Length Encodings OverflowCount Value Dmask Encodings Umask Encodings Event Select Enable Source Disable SourceReload Control 2 SDC FSBDPMD1,0 System Bus Performance Monitor Data Registers 3.1 PMD10 Performance Monitoring Data Register 3 PXB3.2 PMR10 Performance Monitoring Response Count Data Cycles Reload Mode3.3 PME10 Performance Monitoring Event Selection Initiating Agent Selection 4 GXB AGPPMD0,1 AGP Performance Monitor Data Registers Percon Performance Monitor Control Register Pcipmd PCI Performance Monitor Data RegistersEvent 1 Input Event 0 Input AGPPMC0,1 AGP Performance Monitor Configuration RegisterPipe or Sideband Request Mask EVENT1 Count Enable Pcipmc PCI Performance Monitor Configuration RegisterInitiating Agent Disable Source Data Transfer and Transaction Qualifier PCIWXBPMC0 PCI Performance Monitor Configuration Register5 WXB Issuing Agent Qualifier Interrupt Related Registers PCIWXBPMC1 PCI Performance Monitor Configuration RegisterXtprs External Task Priority Registers 2.1 I/O Register Select Register FEC00000h Address Name Access Default ValuePID PCI Memory-mapped Registers Memory-Mapped Register Summary XAPIC EOI Register FEC00040h PID Indirect Access Registers2.2 I/O Window Register FEC00010h I/O Window Register Format 3.1 I/O xAPIC ID Register 00h Offset Name Access Default ValueRTE Memory-mapped Register Summary Cont’d I/O Apic ID Register Format 3.2 I/O xAPIC Version Register 01h3.3 I/O xAPIC Arbitration ID Register 02h I/O xAPIC Version Register Format I/O xAPIC Arbitration ID Register Format Bits Sapic Mode Apic Mode Description Name3.4 I/O xAPIC RTE 10h-8Fh 10. I/O xAPIC RTE Format Sapic Mode Apic Mode Description Name 10. I/O xAPIC RTE Format Cont’d Destination Vector Coherency System ArchitectureProcessor Coherency PCI Coherency OrderingAGP Coherency WXB Arbitration at the PCI Bus WXB ArbitrationArbitration for Inbound Transactions Processor Locks Big-endian SupportIndivisible Operations Arbitration for Outbound Transactions Atomic Reads Inbound PCI LocksAtomic Writes Locks with AGP Non-coherent Traffic Interrupt Delivery WXB PCI Hot-Plug Support Slot Power-up and Enable Slot Power-down and Disable System Architecture Memory Map System Address MapCompatibility Region System Firmware System Memory Address Space Low Extended Memory Region Medium Extended Memory Region Re-mapped Memory Areas High Extended Memory above 4GVariable GAP I/O Address Map Itanium Processor and Chipset-specific Memory Space System I/O Address Space Devices View of the System Memory Map High PXB must ignore GXB must BINIT# after Gart Address Disposition Legal and Illegal Address DispositionAddress Range Outbound Inbound Dest. Decision Above TOM Address Disposition Cont’dMain memory if present above 4 GB Binit System Address Map Organization General Memory CharacteristicsMemory Subsystem System Maximum Memory Configuration Using Two Cards Dimm Types Minimum/Maximum Memory Size per ConfigurationTechnology & Configuration Size Double Number Memory Size Interleaving/Configurations Address Interleaving Non-uniform Memory Configurations Summary of Configuration RulesBandwidth Auto Detection Supporting FeaturesMemory Subsystem Clocking Removing a Bad Row Scrubbing Time Hardware InitializationMemory Scrubbing Memory Size Time to Scrub Memory Subsystem Integrity Data Integrity and Error HandlingSystem Bus PCI Buses DramExpander Buses 5 AGP Memory ECC Routing Usage of First-error and Next-errorData Poisoning BERR#/BINIT# Generation Masked BitsINTREQ# XBINIT# SAC/SDC ErrorsData ECC or Parity Errors XSERR# System Bus Errors SAC to SDC Interface Errors SAC to MAC Interface Errors 5 SDC/Memory Card Interface Errors 6 SDC/System Bus Errors Error DeterminationSDC Internal Errors SAC Address on an Error SDC Logging Registers Special Notes on Usage of SECTID, DEDTID, Fsetid Registers Multiple Errors Clearing Errors1 SAC/SDC Error Clearing SDC Multiple Errors ERR ERR Single Errors with Multiple Reporting SAC Multiple ErrorsError Anomalies Data Flow Errors SAC Error Flow on Data Error Conditions Table of Errors SAC to SDC Interface Errors Error CasesSystem Bus ADD/CMND Error Cases Cont’d Internal SDC Error PXB Errors Detected as PCI Master PXB as Master PCI IntegrityPCI Bus Monitoring Master Abort PXB as Target Target Retry GXB Error FlowTarget Abort GXB Error Signals GXB Errors Gart Interface Errors Multiple Errors GXB Error Flow Integrity WXB Data Integrity and Error HandlingUsage of First Error and Next Error Registers Data Parity Poisoning Supported Error Escalation to XBINIT#a Error Mask BitsError Steering/Signaling Abbreviation Error SERR# Generation Supported Error Escalation to SERROUT#aSupported Error Escalation to PA/BINTRQ# Escalation INTRQ# Interrupt Error Determination and LoggingXBINIT# Generation Error Conditions WXB as Bus Master WXB as Target Other Violations System Error Signaled PCI Interface ErrorsDiscard Timer Expiration AGP Subsystem Graphics Address Relocation Table Gart 22b 12b24b 14b Gart Implementation Gart Entry Format for 4kB Pages Gtlb Programming GartSizes Parity SGW# CoherencySE2 ADSC# ADSP# ADV# LBO# SB# SW# Interrupt Handling 4.1 3.3V AGP 1X and 2X Mode CompatibilityAGP Traffic Addresses Used by the Graphics Card Traffic Priority Coherency, Translation and Types of AGP Traffic Processor Locks and AGP Traffic Ordering RulesCoherency for AGP/PCI Streams PCI Semantics Traffic Address FaultsAddress Alignment and Transfer Sizes Inbound Reads PCI Stream Read Prefetching Inbound Delayed Read Matching RulesInbound Reads Directed To Memory Inbound I/O Reads Delayed Read Matching CriteriaCommand Address BEs Inbound Writes Outbound Reads Retry/Disconnect ConditionsOutbound Writes Burst Write Combining Modes Transfer Data Length Combining Supported Used ModeFast Back-to-Back Transactions 1st write 2nd write 3rd write Transferred as Inbound Read Prefetching LatencyGXB Address Map Bandwidth Estimates for Various Request Sizes AGP Subsystem AGP Subsystem Ihpc Configuration Registers WXB Hot-Plug Ihpc Configuration Register Space VID Vendor Identification Register Number List for the Ihpc PCI Register DescriptionsDid Device Identification Register Pcicmd PCI Command Register Pcists PCI Status Register RID Revision Identification Register CLS Cache Line Size MLT Master Latency Timer RegisterClass Class Register HDR Header Register SID Subsystem ID Base AddressSvid Subsystem Vendor Identification Interrupt Line Interrupt Pin Miscellaneous Hot-Plug ConfigurationHot-Plug Slot Identifier Switch Change Serr Status Hot-Plug FeaturesPower Fault Serr Status Ihpc Memory Mapped Registers Memory Access IndexMemory Mapped Register Access Port Arbiter Serr Status Ihpc Memor Mapped Register Space M66EN Slot Enable Number List for Ihpc Memory Mapped Register Descriptions Hot-Plug Miscellaneous LED Control Hot-Plug Interrupt Input and Clear Hot-Plug Interrupt Mask Serial Input Byte Data General Purpose Output Serial Input Byte PointerHot-Plug Non-interrupt Inputs Slot Power Control Hot-Plug Switch Interrupt Redirect EnableExtended Hot-Plug Miscellaneous Mnemonic Register Register Access PCI / LPC / FWH ConfigurationPCI Configuration Registers Function IFB Register Mapping Classc BiosenPcists Hedt IDE Configuration PCI Configuration Registers-Function 1 IDE Interface PCI Configuration Registers-Function 2 USB Interface Universal Serial Bus USB ConfigurationConfiguration Offset Mnemonic Register SMBus Controller Configuration SMBus Configuration Registers Function IFB Register Mapping CD-ROM Auto RUN Feature of the OS Usage of 1MIN Timer in Power ManagementUsage of the SW SMI# Timer IFB Usage Considerations Disabled Enabled Ultra DMA ConfigurationReserved Secondary Primary Drive Ultra DMA Mode Enable SSDE1 SSDE0 PSDE1 PSDE0 Capability Word Bits Field Offset Determining a Drive’s Transfer Rate CapabilitiesOverview Ultra DMA Fields that Indicate Ultra DMA Drive Capabilities DMA Capability Word BitsPIO Determining a Drive’s Best Ultra DMA Capability Capability Word Bits Field 150 Minimum Multi Word DMA Transfer Cycle Time per Capability Word Offset Bits Field10-6 Drives Reported DMA Drive’s Best DMA Mode Cycle Time Determining a Drive’s Best PIO Capability Drives Reported PIO Drive’s Best PIO Mode Drive PIO Capability as a Function of Cycle Time IFB Drive Mode Based on DMA/PIO Capabilities IFB Timing Settings10.5.6.1 DMA/PIO Timing Settings Mode Yes Disabled Enabled DMA Mode Iordy If fixed disk DMA Iordy IDE 10. Ultra DMA Timing Value Based on Drive Mode Drive Configuration for Selected TimingsUltra DMA Timing Settings DMA/PIO Timing Values Based on Piix Cable Mode/System Speed Drive’s Selected PIO Speed Capability 12. PIO Transfer/Mode Values10-12 Settings Checklist 13. Drive Capabilities Checklist 14. IFB Settings Checklist Example ConfigurationsExample #1 Ultra DMA/33 Configuration Register Type Offset Value Comments 4A-4Bh 0002h Ultra DMA mode config Example #3 Non Ultra DMA/33 Drive Configuration40-41h E377h Mode config. for Primary IDE Timing Register 44h 0Bh Ultra DMA Control Register 4A-4Bh 0000h Ultra DMA System Software Considerations10-16 Intel 460GX Chipset Software Developer’s Manual 10-17 Bit Description Bit Description Reserved. This bit is hardwired toBMISX-Bus Master IDE Status Register I/O Completed or halted USB Resume Enable Bit Bit Type Description 10-20 VID-Vendor Identification Register Function LPC/FWH Interface ConfigurationDID-Device Identification Register Function PCICMD-PCI Command Register Function PCISTS-PCI Device Status Register Function HEDT-Header Type Register Function RID-Revision Identification Register FunctionCLASSC-Class Code Register Function Bit Acpi Base Address Function Acpi Enable FunctionSCI IRQ Routing Control BIOSEN-BIOS Enable Register Function PIRQRCAD-PIRQx Route Control Registers Function SerIRQC-Serial IRQ Control Register Function TOM-Top of Memory Register Function MSTAT-Miscellaneous Status Register Function Deterministic Latency Control Register Function MGPIOC-Muxed Gpio Control Function PDMACFG-PCI DMA Configuration Resister Function OBits Description RTCCFG-Real Time Clock Configuration Register Function Base Offset Channel LPC COM Decode Ranges Function Gpio Enable FunctionGpio Base Address Function Bits Decode Range 011 LPC FDD/LPT Decode Ranges Function000 110 220 233 240 253 260 273 280 293 LPC Sound Decode Ranges FunctionLPC Generic Decode Range Function 11-12 Reserved. This bit must be a LPC Enables FunctionFirmware Hub FWH Decode Enable Register 1413 Reserved Firmware Hub FWH Select Register PCI to LPC I/O Space Registers Test Mode RegisterDcom-Dma Command Register I/O DMA Registers Dcm-Dma Channel Mode Register I/O Dr-Dma Request Register I/O RWAMB-Read / Write All Mask Bits I/O WSMB-Write Single Mask Bit I/OBit Description Reserved. Must be Ds-Dma Status Register I/O DBADDR-DMA Base and Current Address Registers I/O DLPAGE-DMA Low Page Registers I/O When counting down a DMA transferDBCNT-Dma Base and Current Count Registers I/O DCBP-Dma Clear Byte Pointer Register I/O Dmc-Dma Master Clear Register I/O 11.2.2.1 Icw1-Initialization Command Word 1 Register I/OInterrupt Controller Registers Dclm-Dma Clear Mask Register I/O 11.2.2.3 Icw3-Initialization Command Word 3 Register I/O 11.2.2.2 Icw2-Initialization Command Word 2 Register I/OBit Description Reserved. Must be programmed to all 0s 11.2.2.6 Ocw1-Operational Control Word 1 Register I/O 11.2.2.4 Icw3-Initialization Command Word 3 Register I/O11.2.2.5 Icw4-Initialization Command Word 4 Register I/O 11-22 11.2.2.7 Ocw2-Operational Control Word 2 Register I/O 11.2.2.8 Ocw3-Operational Control Word 3 Register I/O Elcr1-Edge/Level Control Register I/O Elcr2-Edge/Level Control Register I/O Counter/Timer RegistersTcw-Timer Control Word Register I/O Bit Decription 5. When bit 2=0, status and/or count will not be latched Latched. When bit 4=1, the status will not be latched5. When bit 3=0, status and/or count will not be latched 5. When bit 1=0, status and/or count will not be latched TMRSTS-Timer Status Registers I/O TMRCNT-Timer Count Registers I/O NMI Registers Nmisc-Nmi Status and Control Register I/O RTCD-Real-time Clock Data Register I/O NMI Enable. Used by IFB NMI logicReal Time Clock Registers Used for NMI enabling/disabling. See description in Section RTCEI-Real-time Clock Extended Index Register I/O Advanced Power Management APM RegistersAPMC-Advanced Power Management Control Port I/O RTCED-Real-time Clock Extended Data Register I/O Power Management 1 Status APMS-Advanced Power Management Status Port I/OAcpi Registers States can be supported in external logic Power Management 1 EnablePower Management 1 Control 11-32 General Purpose 0 Status Power Management 1 TimerBit Description Bits Mode 3124 Reserved 230 1512 Reserved General Purpose 0 EnablePower up, this bit is set to ‘1’ CF9 write SMI Registers General Purpose 1 EnableGeneral Purpose 1 Status Status Register is set Global Control and EnablePort at B2h in I/O space Thrmsts bit GPIO8 General Purpose I/O RegistersGlobal Status Register GPIO7 GP Output GP Data 159 Reserved GP TTL1916 Bit is set GP Lock GP BlinkGP Invert GP Core GP SMIGP Pulse GP Pull-up 11-42 Configuration Mnemonic Register IDE ConfigurationPCI Configuration Registers Function IDE Controller Register Descriptions PCI Function Parity Error Response. This bit is hardwired to SERR# Enable. This bit is hardwired toWait Cycle Control. This bit is hardwired to VGA Palette Snoop. This bit is hardwired to SERR# Status. Read as By writing a 1 to this bit BMIBA-Bus Master Interface Base Address Register Function MLT-Master Latency Timer Register FunctionBus Master interface registers and correspond to AD154 SID-Subsystem ID Function SVID-Subsystem Vendor ID FunctionIDETIM-IDE Timing Register Function SIDETIM-Slave IDE Timing Register Function DMACTL-Synchronous DMA Control Register Function Bit Description Reserved SDMATIM-Synchronous DMA Timing Register Function IDE Controller I/O Space Registers BMICx-Bus Master IDE Command Register I/OUltra DMA/33 Timing Mode Settings Ultra DMA/33 Timing Modes BMISx-Bus Master IDE Status Register I/O Is equal to the IDE device transfer size Interrupt/Activity Status Combinations312 12-12 PCI Configuration Registers-Function Universal Serial Bus USB ConfigurationUsbren Bit Description 1510 Reserved. Read USB Host Controller Register Descriptions PCI FunctionReserved. Read as Resets STA to 0 by writing a 1 to this bit Reserved. Read as 0’s Register in Function This field13-4 USBBA-USB I/O Space Base Address Function INTLN-Interrupt Line Register Function SBRNUM-Serial Bus Release Number Function INTPN-Interrupt Pin FunctionMiscellaneous Control Function LEGSUP-Legacy Support Register Function Appropriate enable bits are set Default to 1 for compatibility with older USB softwareNeeds to be serviced later Accesses that are part of the sequence USBCMD-USB Command Register I/O USBREN-USB Resume EnableUSB Host Controller I/O Space Registers Stop=0, the Frnum register can be reprogrammed Run/Stop, Debug Bit InteractionSwdbg Bit Run/Stop Bit Operation By Software or Hardware Interrupt is generated to the system USBINTR-USB Interrupt Enable Register I/OUSBSTS-USB Status Register I/O Register = FLBASEADD-Frame List Base Address Register I/O Address signalsFRNUM-Frame Number Register I/O SOFMOD-Start of Frame SOF Modify Register I/O PORTSC-Port Status and Control Register I/O EOF2 time See of the USB Specification X0 DisableAsserted, the corresponding port is disabled Register define the hub states as follows 13-14 Class Code 0C-1Fh Reserved SM Bus Controller ConfigurationSM Bus Configuration Registers Function Base Address Register Shutdown special cycle System Management Register Descriptions14-2 STA to 0 by writing a 1 to this bit SMBBA-SMBus Base Address Function 14-4 Host Configuration Interrupt pin PIRQB# is used Smbshdw1-SMBus Slave Shadow Port 1 Function Smbslvc-SMBus Slave Command FunctionSMBus I/O Space Registers Smbshdw2-SMBus Slave Shadow Port 2 Function Smbslvsts-SMBus Slave Status Register I/O Transaction errors are caused bySmbhststs-SMBus Host Status Register I/O Position Smbhstcnt-SMBus Host Control Register I/O Smbhstadd-SMBus Host Address Register I/O Smbhstcmd-SMBus Host Command Register I/OCommand field of SMBus host transaction Smbhstdat0-SMBus Host Data 0 Register I/O Smbblkdat-SMBus Block Data Register I/O Smbhstdat1-SMBus Host Data 1 Register I/OSmbslvcnt-SMBus Slave Control Register I/O 14.3.9.2 10.3.11.smbslvevt-SMBus Slave Event Register I/O 14.3.9.1 Smbshdwcmd -SMBus Shadow Command Register I/OSmbslvdat-SMBus Slave Data Register I/O Address 10h or one of the slave shadow port addresses 14-12 PCI Interface PCI/LPC Bridge DescriptionInterrupt Controller Programming the Interrupt Controller Initialization Command Words ICWs15-2 End of Interrupt Operation Operation Command Words OCWsAutomatic End of Interrupt Aeoi Mode End of Interrupt EOI Modes of Operation Fully Nested ModeSpecial Fully Nested Mode Automatic Rotation Equal Priority Devices Poll Command Cascade ModeSpecific Rotation Specific Priority Interrupt Masks Edge and Level Triggered ModeSpecial Mask Mode Masking on an Individual Interrupt Request Basis Reading the Interrupt Controller Status Interrupt Steering Serial Interrupts Quiet Active ModeContinuous Idle Mode Protocol Data Frame Number Usage # Clocks Past Start Stop FrameSerirq Frames 3222 Programming the Interval Timer Timer/Counters15-10 Interval Timer Control Word Format Write Operations Counter I/O Port Read Counter Latch CommandRead Operations 15-12 Read Back Command Real Time Clock RTC Standard RAM Bank RTC Registers and RAMIndex Address Name 1 Invalid 0 Invalid 15.5.1.1 Register a90625 ms 8125 ms 15.5.1.3 Register C 15.5.1.2 Register BRSMRST# Lockable RAM Ranges RTC Update CycleRTC Interrupts 15.5.1.4 Register D 15-18 Overview IFB Power ManagementIFB Power States and Consumption Acpi State Description 16.2.2 SMI# Generation IFB Power PlanesPower Plane Descriptions Causes of SMI# Causes of SCI# SCI GenerationSleep States SCI Event Comment Acpi Bits Not Implemented in IFB Acpi Bits Not Implemented by IFBEntry/Exit for the S4 and S5 States Offset Register Name/Function Comment Action after Power Returns Handling of Power Failures in IFBS5 Wake Event Comment 16-6