Ultra DMA Configuration, SSDE1 SSDE0 PSDE1 PSDE0 | Intel 460GX

IFB Usage Considerations

into the system firmware by the vendor. This reporting will make these register locations safe and the OS will not use these locations randomly if a PNP conflicting device is relocatable in those I/O or memory locations. These locations also got to be reported to the OS whenever the OEM sends the systems for their WHQL suite test.

10.5Ultra DMA Configuration

The following registers are programmed in systems that contain devices that implement the Ultra DMA Protocol. These registers allow Ultra DMA to be used when PCI Bus Master IDE operation is initiated by the device driver.

10.5.1UDMAC–Ultra DMA Control Register (IFB Function 1 PCI Configuration Offset 48h)

7	6	5	4	3	2	1	0

Reserved				Secondary	Secondary	Primary	Primary
				Drive 1	Drive 0	Drive 1	Drive 0
				Ultra DMA	Ultra DMA	Ultra DMA	Ultra DMA
				Mode	Mode	Mode	Mode
				Enable	Enable	Enable	Enable
				(SSDE1)	(SSDE0)	(PSDE1)	(PSDE0)

				0: Disabled	0: Disabled	0: Disabled	0: Disabled
				1: Enabled	1: Enabled	1: Enabled	1: Enabled

10.5.2UDMATIM–Ultra DMA Timing Register (IFB Function 1 PCI Configuration Offsets 4A-4Bh)

15	14	13		12	11	10	9		8

Reserved		Secondary Drive 1			Reserved		Secondary Drive 0
		Ultra DMA Cycle Time					Ultra DMA Cycle Time
		(SCT1)					(SCT1)

		00: CT=4 clks, RP=6 clks					00: CT=4 clks, RP=6 clks
		01: CT=3 clks, RP=5 clks					01: CT=3 clks, RP=5 clks
		10: CT=2 clks, RP=4 clks					10: CT=2 clks, RP=4 clks
		11: Reserved					11: Reserved

7	6	5		4	3	2	1		0

Reserved		Primary Drive 1			Reserved		Primary Drive 0
		Ultra DMA Cycle Time					Ultra DMA Cycle Time
		(PCT1)					(PCT1)

		00: CT=4 clks, RP=6 clks					00: CT=4 clks, RP=6 clks
		01: CT=3 clks, RP=5 clks					01: CT=3 clks, RP=5 clks
		10: CT=2 clks, RP=4 clks					10: CT=2 clks, RP=4 clks
		11: Reserved					11: Reserved

10-2	Intel® 460GX Chipset Software Developer’s Manual

Image 172

Intel 460GX manual Ultra DMA Configuration, Reserved Secondary Primary Drive Ultra DMA Mode Enable, SSDE1 SSDE0 PSDE1 PSDE0

Contents

Intel 460GX Chipset System Software Developer’s Manual Intel 460GX Chipset System Software Developer’s Manual Contents Coherency 10.1 Latency 10-1 11-8 13.2.4 Figures Tables 12-11 Introduction System Overview Intel 460GX Chipset Components Component OverviewName Function Product Features Itanium Processor System Bus Support Dram Interface Support PXB FeaturesI/O Support RAS Features GXB Features Other Platform Components Reference Documents1 I/O & Firmware Bridge IFB Programmable Interrupt Device PID Revision History Date Description June Initial release Introduction Access Mechanism Register Descriptions Access Restrictions PartitioningDevice Mapping on Bus CBN Device Default Upon Reset Register AttributesReserved Bits Defined in Registers Reserved or Undefined Register Locations Configaddress Configuration Address Register I/O Mapped RegistersConsistency Gart Programming Region Error Handling Registers Configdata Configuration Data Register1 SAC 1.1 Bits Description Disable 1.21.3 Valid Ferrsac First Error Status Register Nerrsac All Error Status Register Saferr System Address on First Error Biuitid BIU Itid Register Biudata BIU Data Register Address bits 2 SDC 2.1 SEC0DFERR Data on First Memory Card B SEC2.2 SEC0ECCFERR ECC on First Memory Card B SEC 2.3 SEC0TXINFOFERR Txinfo on First Memory Card B SEC 2.4 DED0DFERR Data on First Memory Card B DED 2.5 DED0ECCFERR ECC on First Memory Card B DED2.6 DED0TXINFOFERR Txinfo on First Memory Card B DED 2.7 SEC1DFERR Data on First Memory Card a SEC 2.9 SEC1TXINFOFERR Txinfo on First Memory Card a SEC 2.8 SEC1ECCFERR ECC on First Memory Card a SEC2.10 DED1DFERR Data on First Memory Card a DED 2.11 DED1ECCFERR ECC on First Memory Card a DED Sdcferr First Error Status Register2.12 DED1TXINFOFERR Txinfo on First Memory Card a DED 22 ’Forward’ Underflow Card a Right Stack Error FR1 21 ’Forward’ Underflow Card a Left Stack Error FL115 ’Forward’ Underflow Card B Right Stack Error FR0 14 ’Forward’ Underflow Card B Left Stack Error FL0 Pcmdferr Command on First Pcmd Parity Error Sdcnerr SDC Next Error Status RegisterPitidferr Data on First Pitid Parity Error Dpbrleferr Private Data Bus Receive Length Error Sdcrspferr Response on First Sdcrsp ErrorECCMSK0 ECC Mask Register Card B ECCMSK1 ECC Mask Register Card a ParMskP PB Parity Mask and IB Correction Enable RegisterEccmskf ECC Mask Register Pvdparferr Parity on First PVD Parity Error Pvddferr Data on First PVD Parity ErrorPvdtxinfoferr Txinfo on First PVD Parity Error Secfdferr Data on First System Bus SEC Secfeccferr ECC on First System Bus SECSecftxinfoferr Txinfo on First System Bus SEC Dedfdferr Data on First System Bus DED Ferrmac First Error Status Register Que-Overflow Error3 MAC Dedfeccferr ECC on First System Bus DED Errsts Error Status Register Cmndferr Command on First Error4 PXB Errcmd Error Command Register Ferragp First Error Status Register for AGP 5 GXB5.1 Ferrpci Ferrgart First Error Status Register for Gart Nerragp Next Errors Status Register for AGP Pderr PCI Data First Error Pacerr PCI Address & Cmd First ErrorNerrgart Nepci Register Records an PCI Bus Error Flag Fepci Register Records an PCI Bus Error Flag6 WXB Bits Description Intrq Asserted Flag Fepci PCI Bus First Error Status Register Nepci PCI Bus Next Error Status Register Fepcial PCI First Error Address/Command Log Fepcidl PCI First Error Data LogPerformance Monitor Registers 6764 C/BE30 6332 AD6332 310 AD310 Overflow Count ValueLength Encodings Dmask Encodings Umask Encodings Event Select Enable Source Disable SourceReload Control 2 SDC FSBDPMD1,0 System Bus Performance Monitor Data Registers 3.1 PMD10 Performance Monitoring Data Register 3 PXB3.2 PMR10 Performance Monitoring Response Reload Mode 3.3 PME10 Performance Monitoring Event SelectionCount Data Cycles Initiating Agent Selection 4 GXB AGPPMD0,1 AGP Performance Monitor Data Registers Percon Performance Monitor Control Register Pcipmd PCI Performance Monitor Data RegistersEvent 1 Input Event 0 Input AGPPMC0,1 AGP Performance Monitor Configuration RegisterPipe or Sideband Request Mask EVENT1 Count Enable Pcipmc PCI Performance Monitor Configuration RegisterInitiating Agent Disable Source PCIWXBPMC0 PCI Performance Monitor Configuration Register 5 WXBData Transfer and Transaction Qualifier Issuing Agent Qualifier Interrupt Related Registers PCIWXBPMC1 PCI Performance Monitor Configuration RegisterXtprs External Task Priority Registers Address Name Access Default Value PID PCI Memory-mapped Registers2.1 I/O Register Select Register FEC00000h Memory-Mapped Register Summary PID Indirect Access Registers 2.2 I/O Window Register FEC00010hXAPIC EOI Register FEC00040h I/O Window Register Format 3.1 I/O xAPIC ID Register 00h Offset Name Access Default ValueRTE Memory-mapped Register Summary Cont’d 3.2 I/O xAPIC Version Register 01h 3.3 I/O xAPIC Arbitration ID Register 02hI/O Apic ID Register Format I/O xAPIC Version Register Format Bits Sapic Mode Apic Mode Description Name 3.4 I/O xAPIC RTE 10h-8FhI/O xAPIC Arbitration ID Register Format 10. I/O xAPIC RTE Format Sapic Mode Apic Mode Description Name 10. I/O xAPIC RTE Format Cont’d Destination Vector Coherency System ArchitectureProcessor Coherency PCI Coherency OrderingAGP Coherency WXB Arbitration at the PCI Bus WXB ArbitrationArbitration for Inbound Transactions Big-endian Support Indivisible OperationsProcessor Locks Arbitration for Outbound Transactions Inbound PCI Locks Atomic WritesAtomic Reads Locks with AGP Non-coherent Traffic Interrupt Delivery WXB PCI Hot-Plug Support Slot Power-up and Enable Slot Power-down and Disable System Architecture Memory Map System Address MapCompatibility Region System Firmware System Memory Address Space Low Extended Memory Region Medium Extended Memory Region Re-mapped Memory Areas High Extended Memory above 4GVariable GAP I/O Address Map Itanium Processor and Chipset-specific Memory Space System I/O Address Space Devices View of the System Memory Map High PXB must ignore GXB must BINIT# after Gart Address Disposition Legal and Illegal Address DispositionAddress Range Outbound Inbound Dest. Decision Address Disposition Cont’d Main memory if present above 4 GBAbove TOM Binit System Address Map General Memory Characteristics Memory SubsystemOrganization System Maximum Memory Configuration Using Two Cards Minimum/Maximum Memory Size per Configuration Technology & Configuration SizeDimm Types Double Number Memory Size Interleaving/Configurations Address Interleaving Non-uniform Memory Configurations Summary of Configuration RulesBandwidth Supporting Features Memory Subsystem ClockingAuto Detection Removing a Bad Row Hardware Initialization Memory ScrubbingScrubbing Time Memory Size Time to Scrub Memory Subsystem Integrity Data Integrity and Error HandlingSystem Bus Dram Expander BusesPCI Buses 5 AGP Memory ECC Routing Usage of First-error and Next-errorData Poisoning BERR#/BINIT# Generation Masked BitsINTREQ# SAC/SDC Errors Data ECC or Parity ErrorsXBINIT# XSERR# System Bus Errors SAC to SDC Interface Errors SAC to MAC Interface Errors 5 SDC/Memory Card Interface Errors 6 SDC/System Bus Errors Error DeterminationSDC Internal Errors SAC Address on an Error SDC Logging Registers Special Notes on Usage of SECTID, DEDTID, Fsetid Registers Multiple Errors Clearing Errors1 SAC/SDC Error Clearing SDC Multiple Errors ERR ERR Single Errors with Multiple Reporting SAC Multiple ErrorsError Anomalies Data Flow Errors SAC Error Flow on Data Error Conditions Table of Errors SAC to SDC Interface Errors Error CasesSystem Bus ADD/CMND Error Cases Cont’d Internal SDC Error PXB Errors Detected as PCI Master PCI Integrity PCI Bus MonitoringPXB as Master Master Abort PXB as Target Target Retry GXB Error FlowTarget Abort GXB Error Signals GXB Errors Gart Interface Errors Multiple Errors GXB Error Flow WXB Data Integrity and Error Handling Usage of First Error and Next Error RegistersIntegrity Data Parity Poisoning Error Mask Bits Error Steering/SignalingSupported Error Escalation to XBINIT#a Abbreviation Error Supported Error Escalation to SERROUT#a Supported Error Escalation to PA/BINTRQ#SERR# Generation Escalation INTRQ# Interrupt Error Determination and LoggingXBINIT# Generation Error Conditions WXB as Bus Master WXB as Target Other Violations System Error Signaled PCI Interface ErrorsDiscard Timer Expiration AGP Subsystem Graphics Address Relocation Table Gart 12b 24b22b 14b Gart Implementation Gart Entry Format for 4kB Pages Programming Gart SizesGtlb Parity SGW# CoherencySE2 ADSC# ADSP# ADV# LBO# SB# SW# 4.1 3.3V AGP 1X and 2X Mode Compatibility AGP TrafficInterrupt Handling Addresses Used by the Graphics Card Traffic Priority Coherency, Translation and Types of AGP Traffic Processor Locks and AGP Traffic Ordering RulesCoherency for AGP/PCI Streams Address Faults Address Alignment and Transfer SizesPCI Semantics Traffic Inbound Reads PCI Stream Read Prefetching Inbound Delayed Read Matching RulesInbound Reads Directed To Memory Delayed Read Matching Criteria Command Address BEsInbound I/O Reads Inbound Writes Outbound Reads Retry/Disconnect ConditionsOutbound Writes Transfer Data Length Combining Supported Used Mode Fast Back-to-Back TransactionsBurst Write Combining Modes 1st write 2nd write 3rd write Transferred as Latency GXB Address MapInbound Read Prefetching Bandwidth Estimates for Various Request Sizes AGP Subsystem AGP Subsystem Ihpc Configuration Registers WXB Hot-Plug Ihpc Configuration Register Space VID Vendor Identification Register Number List for the Ihpc PCI Register DescriptionsDid Device Identification Register Pcicmd PCI Command Register Pcists PCI Status Register RID Revision Identification Register MLT Master Latency Timer Register Class Class RegisterCLS Cache Line Size HDR Header Register Base Address Svid Subsystem Vendor IdentificationSID Subsystem ID Interrupt Line Interrupt Pin Miscellaneous Hot-Plug ConfigurationHot-Plug Slot Identifier Switch Change Serr Status Hot-Plug FeaturesPower Fault Serr Status Memory Access Index Memory Mapped Register Access PortIhpc Memory Mapped Registers Arbiter Serr Status Ihpc Memor Mapped Register Space M66EN Slot Enable Number List for Ihpc Memory Mapped Register Descriptions Hot-Plug Miscellaneous LED Control Hot-Plug Interrupt Input and Clear Hot-Plug Interrupt Mask Serial Input Byte Data General Purpose Output Serial Input Byte PointerHot-Plug Non-interrupt Inputs Slot Power Control Hot-Plug Switch Interrupt Redirect EnableExtended Hot-Plug Miscellaneous PCI / LPC / FWH Configuration PCI Configuration Registers FunctionMnemonic Register Register Access IFB Register Mapping Biosen PcistsClassc Hedt IDE Configuration PCI Configuration Registers-Function 1 IDE Interface PCI Configuration Registers-Function 2 USB Interface Universal Serial Bus USB ConfigurationConfiguration Offset Mnemonic Register SMBus Controller Configuration SMBus Configuration Registers Function IFB Register Mapping Usage of 1MIN Timer in Power Management Usage of the SW SMI# TimerCD-ROM Auto RUN Feature of the OS IFB Usage Considerations Ultra DMA Configuration Reserved Secondary Primary Drive Ultra DMA Mode EnableDisabled Enabled SSDE1 SSDE0 PSDE1 PSDE0 Determining a Drive’s Transfer Rate Capabilities OverviewCapability Word Bits Field Offset Ultra DMA Fields that Indicate Ultra DMA Drive Capabilities DMA Capability Word BitsPIO Determining a Drive’s Best Ultra DMA Capability Capability Word Bits Field 150 Minimum Multi Word DMA Transfer Cycle Time per Capability Word Offset Bits Field10-6 Drives Reported DMA Drive’s Best DMA Mode Cycle Time Determining a Drive’s Best PIO Capability Drives Reported PIO Drive’s Best PIO Mode Drive PIO Capability as a Function of Cycle Time IFB Timing Settings 10.5.6.1 DMA/PIO Timing SettingsIFB Drive Mode Based on DMA/PIO Capabilities Mode Yes Disabled Enabled DMA Mode Iordy If fixed disk DMA Iordy IDE Drive Configuration for Selected Timings Ultra DMA Timing Settings10. Ultra DMA Timing Value Based on Drive Mode DMA/PIO Timing Values Based on Piix Cable Mode/System Speed Drive’s Selected PIO Speed Capability 12. PIO Transfer/Mode Values10-12 Settings Checklist 13. Drive Capabilities Checklist Example Configurations Example #1 Ultra DMA/33 Configuration14. IFB Settings Checklist Register Type Offset Value Comments Example #3 Non Ultra DMA/33 Drive Configuration 40-41h E377h Mode config. for Primary IDE Timing Register4A-4Bh 0002h Ultra DMA mode config 44h 0Bh Ultra DMA Control Register 4A-4Bh 0000h Ultra DMA System Software Considerations10-16 Intel 460GX Chipset Software Developer’s Manual 10-17 Bit Description Reserved. This bit is hardwired to BMISX-Bus Master IDE Status Register I/OBit Description Completed or halted USB Resume Enable Bit Bit Type Description 10-20 VID-Vendor Identification Register Function LPC/FWH Interface ConfigurationDID-Device Identification Register Function PCICMD-PCI Command Register Function PCISTS-PCI Device Status Register Function RID-Revision Identification Register Function CLASSC-Class Code Register FunctionHEDT-Header Type Register Function Bit Acpi Base Address Function Acpi Enable FunctionSCI IRQ Routing Control BIOSEN-BIOS Enable Register Function PIRQRCAD-PIRQx Route Control Registers Function SerIRQC-Serial IRQ Control Register Function TOM-Top of Memory Register Function MSTAT-Miscellaneous Status Register Function Deterministic Latency Control Register Function MGPIOC-Muxed Gpio Control Function PDMACFG-PCI DMA Configuration Resister Function OBits Description RTCCFG-Real Time Clock Configuration Register Function Base Offset Channel Gpio Enable Function Gpio Base Address FunctionLPC COM Decode Ranges Function Bits Decode Range LPC FDD/LPT Decode Ranges Function 000011 110 LPC Sound Decode Ranges Function LPC Generic Decode Range Function220 233 240 253 260 273 280 293 11-12 LPC Enables Function Firmware Hub FWH Decode Enable RegisterReserved. This bit must be a 1413 Reserved Firmware Hub FWH Select Register Test Mode Register Dcom-Dma Command Register I/OPCI to LPC I/O Space Registers DMA Registers Dcm-Dma Channel Mode Register I/O Dr-Dma Request Register I/O RWAMB-Read / Write All Mask Bits I/O WSMB-Write Single Mask Bit I/OBit Description Reserved. Must be Ds-Dma Status Register I/O DBADDR-DMA Base and Current Address Registers I/O When counting down a DMA transfer DBCNT-Dma Base and Current Count Registers I/ODLPAGE-DMA Low Page Registers I/O DCBP-Dma Clear Byte Pointer Register I/O 11.2.2.1 Icw1-Initialization Command Word 1 Register I/O Interrupt Controller RegistersDmc-Dma Master Clear Register I/O Dclm-Dma Clear Mask Register I/O 11.2.2.3 Icw3-Initialization Command Word 3 Register I/O 11.2.2.2 Icw2-Initialization Command Word 2 Register I/OBit Description Reserved. Must be programmed to all 0s 11.2.2.4 Icw3-Initialization Command Word 3 Register I/O 11.2.2.5 Icw4-Initialization Command Word 4 Register I/O11.2.2.6 Ocw1-Operational Control Word 1 Register I/O 11-22 11.2.2.7 Ocw2-Operational Control Word 2 Register I/O 11.2.2.8 Ocw3-Operational Control Word 3 Register I/O Elcr1-Edge/Level Control Register I/O Counter/Timer Registers Tcw-Timer Control Word Register I/OElcr2-Edge/Level Control Register I/O Bit Decription Latched. When bit 4=1, the status will not be latched 5. When bit 3=0, status and/or count will not be latched5. When bit 2=0, status and/or count will not be latched 5. When bit 1=0, status and/or count will not be latched TMRSTS-Timer Status Registers I/O TMRCNT-Timer Count Registers I/O NMI Registers Nmisc-Nmi Status and Control Register I/O NMI Enable. Used by IFB NMI logic Real Time Clock RegistersRTCD-Real-time Clock Data Register I/O Used for NMI enabling/disabling. See description in Section Advanced Power Management APM Registers APMC-Advanced Power Management Control Port I/ORTCEI-Real-time Clock Extended Index Register I/O RTCED-Real-time Clock Extended Data Register I/O Power Management 1 Status APMS-Advanced Power Management Status Port I/OAcpi Registers Power Management 1 Enable Power Management 1 ControlStates can be supported in external logic 11-32 Power Management 1 Timer Bit Description Bits ModeGeneral Purpose 0 Status 3124 Reserved 230 General Purpose 0 Enable Power up, this bit is set to ‘1’1512 Reserved CF9 write SMI Registers General Purpose 1 EnableGeneral Purpose 1 Status Global Control and Enable Port at B2h in I/O spaceStatus Register is set Thrmsts bit General Purpose I/O Registers Global Status RegisterGPIO8 GPIO7 GP Output GP Data GP TTL 1916159 Reserved Bit is set GP Lock GP BlinkGP Invert GP SMI GP PulseGP Core GP Pull-up 11-42 IDE Configuration PCI Configuration Registers FunctionConfiguration Mnemonic Register IDE Controller Register Descriptions PCI Function SERR# Enable. This bit is hardwired to Wait Cycle Control. This bit is hardwired toParity Error Response. This bit is hardwired to VGA Palette Snoop. This bit is hardwired to SERR# Status. Read as By writing a 1 to this bit BMIBA-Bus Master Interface Base Address Register Function MLT-Master Latency Timer Register FunctionBus Master interface registers and correspond to AD154 SID-Subsystem ID Function SVID-Subsystem Vendor ID FunctionIDETIM-IDE Timing Register Function SIDETIM-Slave IDE Timing Register Function DMACTL-Synchronous DMA Control Register Function Bit Description Reserved SDMATIM-Synchronous DMA Timing Register Function BMICx-Bus Master IDE Command Register I/O Ultra DMA/33 Timing Mode SettingsIDE Controller I/O Space Registers Ultra DMA/33 Timing Modes BMISx-Bus Master IDE Status Register I/O Is equal to the IDE device transfer size Interrupt/Activity Status Combinations312 12-12 PCI Configuration Registers-Function Universal Serial Bus USB ConfigurationUsbren Bit Description 1510 Reserved. Read USB Host Controller Register Descriptions PCI FunctionReserved. Read as Resets STA to 0 by writing a 1 to this bit Reserved. Read as 0’s Register in Function This field13-4 USBBA-USB I/O Space Base Address Function INTLN-Interrupt Line Register Function INTPN-Interrupt Pin Function Miscellaneous Control FunctionSBRNUM-Serial Bus Release Number Function LEGSUP-Legacy Support Register Function Default to 1 for compatibility with older USB software Needs to be serviced laterAppropriate enable bits are set Accesses that are part of the sequence USBCMD-USB Command Register I/O USBREN-USB Resume EnableUSB Host Controller I/O Space Registers Run/Stop, Debug Bit Interaction Swdbg Bit Run/Stop Bit OperationStop=0, the Frnum register can be reprogrammed By Software or Hardware USBINTR-USB Interrupt Enable Register I/O USBSTS-USB Status Register I/OInterrupt is generated to the system Register = Address signals FRNUM-Frame Number Register I/OFLBASEADD-Frame List Base Address Register I/O SOFMOD-Start of Frame SOF Modify Register I/O PORTSC-Port Status and Control Register I/O X0 Disable Asserted, the corresponding port is disabledEOF2 time See of the USB Specification Register define the hub states as follows 13-14 SM Bus Controller Configuration SM Bus Configuration Registers FunctionClass Code 0C-1Fh Reserved Base Address Register Shutdown special cycle System Management Register Descriptions14-2 STA to 0 by writing a 1 to this bit SMBBA-SMBus Base Address Function 14-4 Host Configuration Interrupt pin PIRQB# is used Smbslvc-SMBus Slave Command Function SMBus I/O Space RegistersSmbshdw1-SMBus Slave Shadow Port 1 Function Smbshdw2-SMBus Slave Shadow Port 2 Function Transaction errors are caused by Smbhststs-SMBus Host Status Register I/OSmbslvsts-SMBus Slave Status Register I/O Position Smbhstcnt-SMBus Host Control Register I/O Smbhstcmd-SMBus Host Command Register I/O Command field of SMBus host transactionSmbhstadd-SMBus Host Address Register I/O Smbhstdat0-SMBus Host Data 0 Register I/O Smbblkdat-SMBus Block Data Register I/O Smbhstdat1-SMBus Host Data 1 Register I/OSmbslvcnt-SMBus Slave Control Register I/O 14.3.9.1 Smbshdwcmd -SMBus Shadow Command Register I/O Smbslvdat-SMBus Slave Data Register I/O14.3.9.2 10.3.11.smbslvevt-SMBus Slave Event Register I/O Address 10h or one of the slave shadow port addresses 14-12 PCI Interface PCI/LPC Bridge DescriptionInterrupt Controller Programming the Interrupt Controller Initialization Command Words ICWs15-2 Operation Command Words OCWs Automatic End of Interrupt Aeoi ModeEnd of Interrupt Operation End of Interrupt EOI Fully Nested Mode Special Fully Nested ModeModes of Operation Automatic Rotation Equal Priority Devices Poll Command Cascade ModeSpecific Rotation Specific Priority Edge and Level Triggered Mode Special Mask ModeInterrupt Masks Masking on an Individual Interrupt Request Basis Reading the Interrupt Controller Status Interrupt Steering Quiet Active Mode Continuous Idle ModeSerial Interrupts Protocol Stop Frame Serirq FramesData Frame Number Usage # Clocks Past Start 3222 Programming the Interval Timer Timer/Counters15-10 Interval Timer Control Word Format Write Operations Counter Latch Command Read OperationsCounter I/O Port Read 15-12 Read Back Command Real Time Clock RTC Standard RAM Bank RTC Registers and RAMIndex Address Name 1 Invalid 0 Invalid 15.5.1.1 Register a90625 ms 8125 ms 15.5.1.3 Register C 15.5.1.2 Register BRSMRST# RTC Update Cycle RTC InterruptsLockable RAM Ranges 15.5.1.4 Register D 15-18 IFB Power Management IFB Power States and ConsumptionOverview Acpi State Description IFB Power Planes Power Plane Descriptions16.2.2 SMI# Generation Causes of SMI# SCI Generation Sleep StatesCauses of SCI# SCI Event Comment Acpi Bits Not Implemented by IFB Entry/Exit for the S4 and S5 StatesAcpi Bits Not Implemented in IFB Offset Register Name/Function Comment Action after Power Returns Handling of Power Failures in IFBS5 Wake Event Comment 16-6