Register Descriptions

5System Bus Double Bit Error (DEDF)

ECC Double Bit Error Detected on system bus.

4System Bus Single Bit Error (SECF)

ECC Single Bit Error Detected on system bus.

3SDC Card A Double Bit Error (DED1)

ECC Double Bit Error Detected from Memory Card A.

2SDC Card A Single Bit Error (SEC1)

ECC Single Bit Error Detected from Memory Card A.

1SDC Card B Double Bit Error (DED0)

ECC Double Bit Error Detected from Memory Card B.

0SDC Card B Single Bit Error (SEC0)

ECC Single Bit Error Detected from Memory Card B.

2.4.2.14SDC_NERR: SDC Next Error Status Register

Bus CBN, Device Number: 04h

 

 

Address Offset:

84-87h

Size:

32 bits

Default Value:

0000h

Attribute:

Read/Write to Clear

This register records the next error status within the SDC. Writing a ’1’ to this register will clear the bit in both SDC_NERR and the same bit in SDC_FERR.

Bits Description

31:0 See SDC_FERR for bit definitions.

2.4.2.15PCMD_FERR: Command on First PCMD Parity Error

Bus CBN, Device Number:

04h

 

 

Address Offset:

88-8Bh

Size:

32 bits

Default Value:

00h

Attribute:

Read Only, New Value Latched

 

 

 

anytime appropriate FERR register

 

 

 

bit is set

This register records and latches the data associated with the first parity error detected on the PCMD bus.

Bits Description

31:19 reserved(0)

18If set then the error was detected on the 1st half of the double–pumped transfer. Otherwise, these fields contain the information from the 2nd half of the double-pumped transfer.

17

Parity of Error

16:0

PCMD - Private Data Command value of Error.

2.4.2.16PITID_FERR: Data on First PITID Parity Error

Bus CBN, Device Number:

04h

 

 

Address Offset:

8Ch

Size:

8 bits

Default Value:

0h

Attribute:

Read Only, New Value Latched

 

 

 

anytime appropriate FERR register

 

 

 

bit is set

2-16

 

Intel® 460GX Chipset Software Developer’s Manual