Intel 460GX manual ECCMSK1 ECC Mask Register Card a, Eccmskf ECC Mask Register

Register Descriptions

while masked will return an invalid ECC code. To disable testing, the mask value is left at 0h (the default). The mask is a bit-wise XOR with the computed ECC.

Bits Description

7:0 ECC Generation Mask - For 64 bits of data.

2.4.2.20ECCMSK1: ECC Mask Register - Card A

Bus CBN, Device Number:	04h
Address Offset:	C9h	Size:	8 bits
Default Value:	00h	Attribute:	Read/Write

This register is used to test the ECC error detection logic in the memory subsystem for memory card 1. To test, this register is written with a masking function. All subsequent writes into memory will store a masked version of the computed ECC. Subsequent reads of memory locations written while masked will return an invalid ECC code. To disable testing, the mask value is left at 0h (the default). The mask is a bit-wise XOR with the computed ECC.

Bits Description

7:0 ECC Generation Mask - For 64 bits of data.

2.4.2.21ECCMSKF: ECC Mask Register

Bus CBN, Device Number:	04h
Address Offset:	CAh	Size:	8 bits
Default Value:	00h	Attribute:	Read/Write

This register is used to test the ECC error detection logic of the host processor bus. To test, this register is written with a masking function. All subsequent processor reads will received a masked version of ECC code. To disable testing, the mask value is left at 0h (the default). The mask is a bit-wise XOR with the computed ECC.

Bits Description

7:0 ECC Generation Mask - For 64 bits of data.

2.4.2.22ParMskP: PB Parity Mask and IB Correction Enable Register

Bus CBN, Device Number:	04h
Address Offset:	CBh	Size:	8 bits
Default Value:	00h	Attribute:	Read/Write

The first 4 bits of this register are used to test the data parity error detection logic of the private bus. To test, bits 3:0 are written with a masking function. All subsequent private bus reads will receive a masked version of double byte parity. To disable testing, the mask value is left at 0h (the default). The mask is a bit-wise XOR with the computed parity.

Bits 7:4 are used to enable ECC or parity checking for the different busses. Note that the SDC defaults to no parity or ECC checking at power-on.

Bits	Description
7	Private Bus parity detection enable.
6	Front Side Bus ECC correction/detection enable.

2-18 Intel® 460GX Chipset Software Developer’s Manual