Intel 460GX Illegal Address, Bits Description, Bits Description, Bits Description, 3GART Parity Error, 2GART Entry Invalid, 0 Illegal AGP Command

Register Descriptions

Default Value:	00h	Attribute:	Read/Write Clear
Sticky:	Yes	Locked:	No

These registers record and latch the first error detected in the AGP interface.

Bits Description

7:6 reserved (0)

5Lo-priority Read Data Que Parity Error

This is data returned to the graphics card out of the Low-priority buffer.

4Hi-priority Read Data Que Parity Error

This is data returned to the graphics card out of the Hi-priority buffer.

3Use of Pipe with Sideband Enabled2AGP address from graphics card [63:40] not equal to 01AGP Request Queue Overflow

The GXB supports 16 outstanding requests. This bit is set if a new request is sent by the AGP card when the GXB already has 16 requests.

0 Illegal AGP Command2.4.5.4FERR_GART: First Error Status Register for GART

Function Number:	BFN+1
Address Offset:	86h	Size:	8 bits
Default Value:	00h	Attribute:	Read/Write Clear
Sticky:	Yes	Locked:	No

These registers record and latch the first error detected in the AGP interface.

Bits Description

7:4 reserved (0)

3GART Parity Error.2GART Entry Invalid

1Illegal Address (after GART translation) in range between GAPBAS and GAPTOP, or in VGA range and VGAGE is asserted, or directed by MARG to PCI instead of memory, or above TOM.

0 reserved (0)

2.4.5.5NERR_AGP: Next Errors Status Register for AGP

Function Number:	BFN+1
Address Offset:	8Dh	Size:	8 bits
Default Value:	00h	Attribute:	Read/Write Clear
Sticky:	Yes	Locked:	No

This register records all error conditions detected in the AGP interface after the first error. Errors recorded in FERR_AGP are not recorded here.

Bits Description

7:0 See FERR_AGP for definition of these bits.

Intel® 460GX Chipset Software Developer’s Manual 2-25