IDE Configuration

Table 12-2. Ultra DMA/33 Timing Mode Settings

 

 

Ultra DMA/33 Timing Modes

 

Cycle Time Bit Settings

 

 

 

 

Mode 0 (120 ns)

 

Mode 1 (90 ns)

Mode 2 (60 ns)

 

 

 

 

 

 

00

 

01

10

 

 

 

 

 

Table 12-3. DMA/PIO Timing Values Based on IFB Cable Mode and System Speed

 

IORDY

 

IDETIM [15:8]

IDETIM [15:8]

SIDETIM

Resultant

 

 

 

Drive 0 (Master)

 

IFB Drive

Recovery

Drive 0

Pri [3:0]

Cycle Time

Sample

If no Slave

Time

(Master)

Sec [7:4]

Base Operating

Mode

Point

Attached or

(RCT)

If Slave

Drive 1

Frequency and

 

(ISP)

Slave is

 

 

Attached

(Slave)

Cycle Time

2

 

 

 

Mode 01

 

PIO0/

6 clocks

1 clocks

C0h

80h

0

30 MHz: 660ns

Compatible

(Default)

(Default)

 

 

 

33 MHz: 600ns

 

 

 

 

 

 

 

PIO2/SW2

4 clocks

4 clocks

D0h

90h

4

30 MHz: 256ns

 

 

 

 

 

 

33 MHz: 240ns

 

 

 

 

 

 

 

PIO3/MW1

3 clocks

3 clocks

E1h

A1h

9

30 MHz: 198ns

 

 

 

 

 

 

33 MHz: 180ns

 

 

 

 

 

 

 

PIO4/MW2

3 clocks

1 clock

E3h

A3h

B

30 MHz: 132ns

 

 

 

 

 

 

33 MHz: 120ns

 

 

 

 

 

 

 

 

NOTES:

1.Table 12-3assumes that if the attached slave drive is Mode 0 or not present, the SITRE bit is ‘0’.

2.Table 12-3assumes that 25 MHz is not supported as a target PCI system speed. If the DMA Timing Enable Only (DTE) bit has been enabled for that drive, this resultant cycle time applies to data transfers performed with DMA only.

12.3IDE Controller I/O Space Registers

The PCI IDE Function uses 16 bytes of I/O space, allocated via the BMIBA register. All bus master IDE I/O space registers can be accessed as byte, word, or DWord quantities. The description of the 16 bytes of I/O registers follows.

12.3.1BMICx–Bus Master IDE Command Register (I/O)

Address Offset:

Primary Channel–Base + 00h; Secondary Channel–Base + 08h

Default Value:

00h

Attribute:

Read/Write

This register enables/disables bus master capability for the IDE Function and provides direction control for the IDE DMA transfers. This register also provides bits that software uses to indicate DMA capability of the IDE device.

Intel® 460GX Chipset Software Developer’s Manual

12-9