Intel 460GX 6.9Data Flow Errors, Figure 6-1.SAC Error Flow on Data

Data Integrity and Error Handling

Take the case where processor 1 reads a line from memory and there are no errors, and then does a write into its cache. Later processor 2 does a read, getting an IWB. The SAC starts a speculative read for the line before seeing the HITM#. If the data in DRAM has a 2x error on this read the SDC data buffer will be marked as having a 2x error on this line. In this case, assuming the speculative read is done (in some cases the HITM# is seen before the memory cycle is attempted, so no speculative read is done), the IWB data that is written back into memory will be poisoned.

6.9Data Flow Errors

Figure 6-1and Figure 6-2show the data flow and errors that are checked. The SDC will report DRAM errors for either single-bit (S) or double-bit (D) fails. The SDC will never signal that an error was fatal (causing BINIT#). The processor will handle data that it receives with bad ECC. The memory will have bad ECC written to it, if incoming data is bad. Data to the SAC will be handled by the SAC itself. Either the SAC will BINIT# on seeing bad data or it will pass it on to the xXB via an Expander port.

Figure 6-1. SAC Error Flow on Data

System Bus

ITID

Address parity.

Check parity.

Request parity.

Bus protocol checking

RETIREMENT

Check parity.

BUS

.

Pass data with

good/bad parity to

TO

1 parity per 18 bits (16 data and 2 BE)

SDC or Expander (peer).

No checking done.

68b bus

SDC

1 parity per 16 bits (16 data)

From

1 parity per

16b of data

BIU

Pass data from SDC

to Expander bus with

From

1 parity, 16 data,

2b BE

good/bad parity.

SDC

2 BE

From

16b data,

No checking done.

BIU

1Parity

Generate

Check parity on

parity as DP xor

Check outgoing

BE0 xor BE1, not

header and data.

parity from data

18-way XOR

Check for HF.

buffer.

Expander: From xXB Expander: To xXB

6-14 Intel® 460GX Chipset Software Developer’s Manual