Intel 460GX manual Smbslvdat-SMBus Slave Data Register I/O

SM Bus Controller Configuration

Bit	Description
0	Slave Enable (SLV_EN)–R/W.1 = Enable the generation of an interrupt or resume event upon
	an external SMBus master generating a transaction with an address that matches the host
	controller slave port of 10h, a command field which matches the SMBSLVC register, and a
	match of one of the corresponding enabled events in the SMBSLVEVT register. 0 = Disable.

14.3.9.1	10.3.10.smbshdwcmd–SMBus Shadow Command Register (I/O)
	I/O Address:		Base + (09h)
	Default Value:		00h
	Attribute:		Read only
	This register is used to store command values for external SMBus master accesses to the host slave
	and slave shadow ports.
	Bit		Description
	7:0	Shadow Command (SHDW_CMD)–RO.This field contains the command value which was
		received during an external SMBus master access whose address field matched the host slave
		address (10h) or one of the slave shadow port addresses.

14.3.9.210.3.11.smbslvevt–SMBus Slave Event Register (I/O)

I/O Address:	Base + (0Ah)
Default Value:	0000h
Attribute:	Read/Write

This register is used to enable generation of interrupt or resume events for accesses to the host controller’s slave port.

Bit	Description
15:0	SM BUS Slave Event (SMB_SLV_EVT)–R/W.This field contains data bits used to compare
	against incoming data to the SMBSLVDAT register. When a bit in this register is a 1 and the
	corresponding bit in the SMBSLVDAT register is set, then an interrupt or resume event will be
	generated if the command value matches the value in the SMBSLVC register and the access
	was to SMBus host address 10h.

14.3.10smbslvdat–SMBus Slave Data Register (I/O)

I/O Address:	Base + (0Ch)
Default Value:	0000h
Attribute:	Read only

This register is used to store data values for external SMBus master accesses to the shadow ports or the SMBus host controller’s slave port.

Bit	Description
15:0	SLAVE DATA (SMB_SLV_DATA)–RO.This field contains the data value which was transmitted
	during an external SMBus master access whose address field matched one of the slave shadow
	port addresses or the SMBus host controller slave port address of 10h.

Intel® 460GX Chipset Software Developer’s Manual 14-11