Intel 460GX SDC Logging Registers, Special Notes on Usage of SECTID, DEDTID, Fsetid Registers

Data Integrity and Error Handling

After this the error reporting is in the clean state.

After the ITID is found, the actual address is needed. Again this is somewhat indirect. There are 2 locations in the SAC in which the address may be found. One is the Bus Interface Unit’s (BIU) CAM and RAM, and the second is the MIU’s RAM. The BIU’s CAM contains the address for coherent transactions. The RAM contains the address, command and other information. See the register definition for BIUDATA for the bit definitions of the information captured. For the MIU, the RAM contains the address of the transaction before it has been translated into a memory address. This address may have come from the system bus for a processor or a 460GX-initiated coherent access, or it may have come from AGP or other non-coherent source. The RAM/CAM may only be used for coherent transactions. The MIU tracks both coherent and non-coherent transactions. Non-coherent transactions are those sent by an AGP card. Software can simply read the MIU for all transactions. If software reads the MIU and RAM/CAM and gets the same value for the address, then the transaction was coherent and the rest of the RAM/CAM data is valid. If the 2 addresses are different, then software should not read the rest of the RAM/CAM.

To access the system bus’s address, the ITID which was read from one of the registers listed above is written into BIUITID. The write to this register causes the register BIUDATA to be updated with the RAM and CAM contents associated with the ITID written into BIUITID. BIUDATA can be read and the address determined.

To access the memory’s address buffer, the procedure is slightly different. This buffer is directly readable, instead of using the indirect approach used by the BIU. To read the MIU address do:

•Read ITID from one of the registers above:

—If the ITID is less than or equal to 31, then do a configuration read from BUS: CBN,

Device: 1, Function: 2, Address: (80h+4*ITID). This is MEMTID0 register.

—If the ITID is greater than 31, then do a configuration read from BUS: CBN, Device: 1,

Function: 3, Address: (80h+4*(ITID-32)). This is MEMTID1 register.

6.6.1.1Special Notes on Usage of SECTID, DEDTID, FSETID Registers

The SAC’s SECTID, DEDTID and FSETID registers all define bit [7] as a Disable bit. When set, the register will not capture the ITID and the transaction is retired immediately. There is one side- effect that isn’t apparent when setting the Disable bit to ‘1’. Not only is the ITID not captured, the FERR or NERR registers are not set either. Therefore if the Disable bit is a ‘1’, the SAC will not indicate any error, and there will be no interrupt or signal to the system. The SDC is not affected by setting the Disable bit, so it will continue to log the errors.

—If software sets the Disable bit in any of these 3 registers, it is responsible for polling the SDC for errors or accept that the errors will not be reported to the system. It is recommended that the Disable bit be set only for special applications or usage.

6.6.2SDC Logging Registers

The SDC has logging registers to capture single and multiple bit errors on all the interfaces. These are:

•SEC0 - first single-bit ECC error on memory card 0.

•DED0 - first double-bit ECC error on memory card 0.

•SEC1 - first single-bit ECC error on memory card 1.

•DED1 - first double-bit ECC error on memory card 1.

•PVD - first parity error on the private data bus.

•SECF - first single-bit ECC error on the system bus.

6-10 Intel® 460GX Chipset Software Developer’s Manual