Intel 460GX 2.4.4PXB, Bits Description, Bits Description, 0Parity Error - CMND, 6PERR# observed on PCI Bus, 4Parity Error on PCI Address

Register Descriptions

0Parity Error - CMND

Parity Error Detected on SAC-MAC CMND Bus. Look in CMND_FERR Register to isolate. When the error is detected, the MAC will complete those operations which have a RAS pending, and stop. No new RAS cycles will be issued after the parity error and that card is effectively dead.

2.4.3.2CMND_FERR: Command on First Error

Bus CBN, Device Number:	05h,06h	Function Number:	00h,01h
Address Offset:	9Ch	Size:	24 bits
Default Value:	0000h	Attribute:	Read

This register records and latches the data on the SAC-MAC Command Bus for the first error detected.

Bits Description

23:22 reserved (0)

21:19 Row address [2:0]

18:17 Command [1:0]

16:0 MA[16:0]

2.4.4PXB2.4.4.1ERRSTS: Error Status Register

Address Offset:	44h	Size:	8 bits
Default Value:	00h	Attribute:	Read/Write Clear, Sticky

This register records error conditions detected from the PCI bus (not already covered in PCISTS), from the Expander Bus, and performance monitoring events.

The register is sticky through reset; that is, the contents of the register remain unchanged during and following the assertion of X(0,1)RST#. This allows system recovery software invoked following a forced reset to examine the flags to determine the cause of an error. Once set, the flags remain set until explicitly cleared by software or a power-goodreset.

Bits Description

7reserved(0).

6PERR# observed on PCI Bus

This flag is set if the PXB detects the PERR# input asserted, and the PXB was not the asserting agent. This flag may be configured to assert SERR# or PERR# in the ERRCMD register. This bit remains set until explicitly cleared by software writing a 1 to this bit.

5Parity Error on Received PCI Data

This flag is set if the PXB detects a parity error on data being read from the PCI bus. This flag may be configured to assert SERR# or PERR# in the ERRCMD register. This bit remains set until explicitly cleared by software writing a 1 to this bit.

4Parity Error on PCI Address

This flag is set if the PXB detects a parity error on the PCI address. This flag may be configured to assert SERR# in the ERRCMD register. This bit remains set until explicitly cleared by software writing a 1 to this bit.

2-22 Intel® 460GX Chipset Software Developer’s Manual