Intel 460GX manual Error Conditions, WXB as Bus Master

Data Integrity and Error Handling

6.12.8Error Conditions

6.12.8.1WXB as Bus Master

6.12.8.1.1 Master Abort

If the WXB initiates a PCI transaction and no target responds, the WXB will terminate the transaction with a master-abort. The WXB will wait five PCI clocks after asserting FRAME# for a target to respond with DEVSEL#. If no target responds, the WXB will perform a master abort to terminate the cycle on the PCI bus. Special Cycle commands, which are broadcast to all PCI targets, will always be terminated with master abort and, therefore, are never considered an error. Master aborts during other transactions (configuration, memory map, or I/O cycles) also are generally not considered as errors. For writes, a normal completion packet will be returned to the Chipset core. Reads will additionally return all 1’s as data.

When the WXB performs a master abort, it will log the event by setting the PCISTS register’s Received Master Abort (RMA) bit, unless the transaction was a Special Cycle.

6.12.8.1.2 Received Target Disconnect

A PCI target may issue a disconnect to indicate it is unable to respond within the PCI latency guidelines. Disconnect is signaled when the target asserts both STOP# and DEVSEL#. The target controls whether another data transfer may occur by whether TRDY# is asserted when STOP# is asserted. A target disconnect is not usually issued on the first data phase of the transaction. Target disconnects are not considered errors, and are not logged or reported in any way. After a target disconnect, the WXB will deassert its request signal and wait at least two PCI clocks before re- arbitrating for the PCI bus to complete the transfer.

6.12.8.1.3 Received Target Retry

A PCI target may issue a retry to indicate that it is currently unable to process the transaction. Retry is signaled when the target asserts STOP# and DEVSEL# and does not assert TRDY#. Retry is actually a special case of disconnect that occurs before the first data transfer.

After receiving a retry for a transaction, the WXB will deassert its request line and wait at least two PCI clocks before re-arbitrating for the PCI bus to retry the transaction. If the transaction is a write, the WXB will retry the transaction until it succeeds. If the transaction is a read, the WXB will reattempt the transaction until it succeeds, but may allow other reads and writes to pass it. Note, in all of these cases the retries are not considered errors. There is no logging or error reporting of any kind.

6.12.8.1.4 Received Target Abort

A PCI target may issue an abort to indicate that the current transaction should be terminated and should not be attempted again. This is a catastrophic failure. Target abort is signaled when STOP# is asserted and DEVSEL# is deasserted. The WXB will log the target abort by setting the PCISTS register’s Received Target Abort (RTA) bit. The WXB then returns a hard fail response to the Chipset core.

6.12.8.1.5 Data Parity Errors

When the WXB is the PCI bus master, it will check the data parity provided during read data cycles, and watch for the assertion of PERR# during write data cycles. If a parity error is detected, and the PCICMD registers PERRE bit is set, then the PCISTS register’s Detected Parity Error

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