Intel 460GX manual FSBDPMD1,0 System Bus Performance Monitor Data Registers, Overflow

Register Descriptions

01b Disable when counter overflows.

10b Disable on falling edge (Deassertion) of SDC Event 0. 11b Disable on falling edge (Deassertion) of SDC Event 1.

4:3 Enable Source.

Selects event that will enable the performance monitor.

00b Never Enable (in this mode the counter will never count).

01b Enable Always (note that if this setting is used, the disable events in bits [6:5] will only disable counting for one clock, and then the counter resumes. When bits [4:3] are set to ’Enable Always’, the only meaningful setting for bits [6:5] is

’Never Disable’.

10b Enable on rising edge (Assertion) of SDC Event 0.

11b Enable on rising edge (Assertion) of SDC Event 1.

2:0 Reload Control.

Selects event that will control the Reloading of the performance monitor with the value written into the associated PMD1 register.

000b Never Reload.

001b Reload when counter overflows.

010b Reload on SDC Event 0 Asserted.

011b Reload on SDC Event 1 Asserted.

100b Reload on SDC Event 0 Asserting edge.

101b Reload on SDC Event 1 Asserting edge.

2.5.2.2FSB_D_PMD_[1,0]: System Bus Performance Monitor Data Registers

Bus CBN, Device Number: 04h
Address Offset:	A0-A7h, A8-AFh	Size:	64 bits each
Default Value:	0 each	Attribute:	Read/Write

Two performance monitoring counters, with associated event selection and control registers, is provided in the SDC component. These counters may be configured to track system bus events. Event detection may be configured to increment a counter, affect performance monitoring pins, and issue an interrupt request on counter overflow.

The value written to this address, loads the counter and is also saved in a reload register. Each counter can be configured to reload the data when it overflows.

The FSB_D_PMD_[1,0] registers hold the performance monitoring count values. 39-bits of the counter are used for event counting, the 40th-bit is used as a overflow detection bit. The 39-bit count value allows up to 70 minutes of event collection at 133 MHz. Event selection is controlled by the PMC registers.

Each counter may be stopped/started independently, using the controls available in the associated PMD register.

Bits Description

63:40 reserved(0)

39Overflow

This bit is asserted when the Event Count bit 38 carries into bit 39.

38:0 Count Value

This register contains the Performance Monitor Data Register. You may preset the value of the performance counter by writing to this register. You may read back the value of the performance counter by reading this register.

Intel® 460GX Chipset Software Developer’s Manual 2-35