Intel 460GX Smbhstdat1-SMBus Host Data 1 Register I/O, Smbblkdat-SMBus Block Data Register I/O

SM Bus Controller Configuration

14.3.7smbhstdat1–SMBus Host Data 1 Register (I/O)

I/O Address:	Base + (06h)
Default Value:	00h
Attribute:	Read/Write

This register is transmitted by the SMBus controller host interface in the Data1 field of the SMBus protocol.

Bit	Description
7:0	SMBus Data 1 (SMBD1)–R/W.This register should be programmed with the value to be
	transmitted in the Data1 field of an SMBus host interface transaction.

14.3.8smbblkdat–SMBus Block Data Register (I/O)

I/O Address:	Base + (07h)
Default Value:	00h
Attribute:	Read/Write

Reads and writes to this register are used to access the 32 byte block data storage array. An internal index pointer is used to address the array. It is reset to 0 by reading the SMBHSTCNT register. The index pointer then increments automatically upon each access to this register. The transfer of block data into (read) or out of (write) this storage array during an SMBus transaction always starts at index address 0.

Bit	Description
7:0	SMBus Block Data (BLK_DAT)–R/W.This register is used to transfer data into or out of the
	block data storage array.

14.3.9smbslvcnt–SMBus Slave Control Register (I/O)

I/O Address:	Base + (08h)
Default Value:	00h
Attribute:	Read/Write

The control register is used to enable SMBus controller slave interface Functions.

Bit	Description
7	SLV_INT_EN: When set to a ‘1’, the generation of a slave interrupt or SMI# based on a master
	SMB device generating an access to the host controller’s slave port is enabled. The slave port
	will set the SLV_STS bit in the Slave Status register (offset 01h). The data will placed in the
	Slave Data register (offset 0Ah).
6:3	Reserved.
2	SMBus Shadow Port 2 Enable(SHDW2_EN)–R/W. SLV_INT_EN and SHDW2_EN =1 will
	enable the generation of an interrupt or resume event upon an external SMBus master
	generating a transaction with an address that matches the SMBSHDW2 register. 0 = Disable.
1	SMBus Shadow Port 1 Enable(SHDW1_EN)–R/W. SLV_INT_EN and SHDW1_EN =1 will
	enable the generation of an interrupt or resume event upon an external SMBus master
	generating a transaction with an address that matches the SMBSHDW1 register. 0 = Disable.

14-10 Intel® 460GX Chipset Software Developer’s Manual