Intel 460GX 11.2.1.9DLPAGE–DMALow Page Registers (I/O), 11.2.1.10DCBP–DmaClear Byte Pointer Register (I/O), 11.2.1.8DBCNT–DmaBase and Current Count Registers (I/O)

LPC/FWH Interface Configuration

11.2.1.8DBCNT–Dma Base and Current Count Registers (I/O)

I/O Address:	DMA Channel 0–001h	DMA Channel 4–0C2h
	DMA Channel 1–003h	DMA Channel 5–0C6h
	DMA Channel 2–005h	DMA Channel 6–0CAh
	DMA Channel 3–007h	DMA Channel 7–0CEh
Default Value:	Undefined (CPURST or Master Clear)
Attribute:	Read/Write

This register determines the number of transfers to be performed. The actual number of transfers is one more than the number programmed in the Current Byte/Word Count Register When the value in the register is decremented from zero to FFFFh, a TC is generated. Auto-initialize can only occur when a TC occurs. If it is not auto-initialized, this register has a count of FFFFh after TC.

For transfers to/from an 8-bit I/O, the Byte/Word count indicates the number of bytes to be transferred. This applies to DMA channels 0-3. For transfers to/from a 16-bit I/O, with shifted address, the Byte/Word count indicates the number of 16-bit words to be transferred. This applies to DMA channels 5-7.

Bit Description

15:0 Base and Current Byte/ Word Count. These bits represent the 16 byte/word count bits used when counting down a DMA transfer.

11.2.1.9DLPAGE–DMA Low Page Registers (I/O)

I/O Address:	DMA Channel 0–087h	DMA Channel 5–08Bh
	DMA Channel 1–083h	DMA Channel 6–089h
	DMA Channel 2–081h	DMA Channel 7–08Ah
	DMA Channel 3–082h
Default Value:	Undefined (CPURST or Master Clear)
Attribute:	Read/Write

This register works in conjunction with the Current Address Register. After an auto-initialization, this register retains the original programmed value. Auto-initialize takes place after a TC.

Bit Description

7:0 DMA Low Page [23:16]. These bits represent address bits [23:16] of the 24-bit DMA address.

11.2.1.10DCBP–Dma Clear Byte Pointer Register (I/O)

I/O Address:	Channels 0-3–00Ch; Channels 4-7–0D8h
Default Value:	All bits undefined
Attribute:	Write Only

Writing to this register executes the Clear Byte Pointer Command. This command is executed prior to reading/writing a new address or word count to the DMA. The command initializes the byte pointer flip-flop to a known state so that subsequent accesses to register contents address upper and lower bytes in the correct sequence. The Clear Byte Pointer Command (or CPURST or the Master Clear Command) clears the internal latch used to address the upper or lower byte of the 16-bit Address and Word Count Registers.

Intel® 460GX Chipset Software Developer’s Manual 11-19