Intel 460GX manual Interrupt Pin, Hot-Plug Slot Identifier, Miscellaneous Hot-Plug Configuration

WXB Hot-Plug

This is a standard PCI configuration register which defines which interrupt request line on the interrupt controller this function’s interrupt pin (see register 3DH) is connected to. The power-up default value is FFh.

8.1.15Interrupt Pin

Address Offset:	3Dh	Size:	8 bits
Default Value:	01h	Attribute:	Read Only

This is a standard PCI configuration register which defines which of the four PCI interrupt pins, INTA# through INTD#, this function is connected to. PCI Hot-Plug is connected to INTA#, making this value hard-wired to 01h.

8.1.16Hot-Plug Slot Identifier

Address Offset:	40h-41h	Size:	16 bits
Default Value:	0000h	Attribute:	Partial Read/Write

This register indicates which slots support hot-plug. Not used by the IHPC, this register is set by the boot ROM for later reference by the hot-plug drivers. This register is also mapped to memory space. System designers are required to follow a convention whereby hot-plug slots are always implemented in sequential PCI device number order. IHPC slot A should be the lowest numbered slot (i.e. the device number in this register).

Bits Description

15:8 reserved(0)

7:4 The PCI device number for the first slot that supports hot-plug.

3:0 Number of hot-plug slots controlled.

8.1.17Miscellaneous Hot-Plug Configuration

Address Offset:	42h-43h	Size:	16 bits
Default Value:	0002h 1	Attribute:	Read/Write, Write-Once, Read-Only

This is a hot-plug specific register used to configure many features of the IHPC.

Bits Description

15Change device ID. Write Once/Read Only. Changes the device ID from 123Fh to 123Eh in order to “hide” the IHPC from industry-standard hot-plug drivers and device enumerators in non-hot-plug systems.

14Inhibit hot-plug registers. Write Once/Read Only. This bit prohibits access to the IHPC registers, effectively disabling the IHPC.

13Enable Power Fault functions. This bit must be set to enable other power-fault related SERR signaling.

12Enable Lock of the Auto Power-Down Disable bit. Write Once/Read Only. This bit should be written to a logic 1 (by firmware) after the Auto-Power-Down Disable bit of the Hot-Plug Miscellaneous register has been written. Once written, this bit causes the Auto-Power-Down Disable bit to be unchangeable until XRST# or PCI reset. This prevents driver software from changing the auto-power-down feature.

1.Bit 0 may be changed to a 1 after Reset in future implementation.

8-8 Intel® 460GX Chipset Software Developer’s Manual