Register Descriptions

18‘Completion’ Command Underflow; MAC B, Stack R (CCBR)

One of these 4 bits is set when the SAC receives a completion from the MAC and the SAC has no outstanding transaction.

17BERR# Observed (BER)

BERR# seen on the system bus. Set whenever BERR# is observed active.

16IOQ Underflow/Overflow (IUE)

Set when the IOQ is empty and the SDC sends out a signal saying it popped something from the top of the queue. Or set when the IOQ is 8 (or 1 when the IOQ depth is set to 1) and an ADS# is seen on the bus.

15reserved(0)14External XBINIT# Active. (XBE)

Set when XBINIT# is seen active. This signal is from an Expander port or other external agent.

13False Retirement (FRE)

Retirement from SDC that doesn’t match an outstanding ITID in the SAC.

12Address above TOM (TE)

Asserted when an address on the system bus is above TOM and not inside the I/O gap below 4 GB.

11Illegal HITM# (IHS)

HITM# on non-memory access.

10Unsupported ASZ[1:0]# (ASE)

Processor access to an address above 64 GB, so that ASZ# = 10b or 11b.

9System Bus Address Parity Error (AE) Parity error on A[36:3]#.8System Bus Request Parity Error (RQE) Parity error on REQ[4:0]#.7PDB ITID Parity Error (IPE)

Parity error on the ITID bus from SDC to SAC.

6Retirement Bus Parity Error (RPE)

Parity error on the retirement bus from the SDC to the SAC.

5Lock# Transaction With No Resources Available (LTE)

Set when a LOCK# transaction occurs and there are no outbound resources available in which to place the lock.

4:1 reserved(0)

0Resource Counter Overflow/Underflow (RCE)

Set if the resource counter has an underflow or overflow.

2.4.1.5NERR_SAC: All Error Status Register

Bus CBN, Device Number:

00h

Function:

1

Address Offset:

44h

Size:

32 bits

Default Value:

000000h

Attribute:

Read/Write Clear

Sticky:

Yes

Locked:

No

This register records all error conditions detected in the SAC/SDC.

Bits Description

31:0 See FERR_SAC for bit definitions.

2-8

Intel® 460GX Chipset Software Developer’s Manual