Intel 460GX manual Contents

Contents

1	Introduction......................................................................................................................			1-1
	1.1	System Overview ...............................................................................................		1-1
		1.1.1	Component Overview............................................................................	1-2
	1.2	Product Features................................................................................................		1-3
	1.3	Itanium™ Processor System Bus Support .........................................................		1-3
	1.4	DRAM Interface Support ....................................................................................		1-4
	1.5	I/O Support .........................................................................................................		1-4
		1.5.1	PXB Features ........................................................................................	1-4
		1.5.2	WXB Features .......................................................................................	1-6
		1.5.3	GXB Features........................................................................................	1-6
	1.6	RAS Features.....................................................................................................		1-6
	1.7	Other Platform Components...............................................................................		1-6
		1.7.1 I/O & Firmware Bridge (IFB)..................................................................		1-6
		1.7.2 Programmable Interrupt Device (PID) ...................................................		1-7
	1.8	Reference Documents........................................................................................		1-7
	1.9	Revision History .................................................................................................		1-7
2	Register Descriptions ......................................................................................................			2-1
	2.1	Access Mechanism ............................................................................................		2-1
	2.2	Access Restrictions ............................................................................................		2-2
		2.2.1	Partitioning ............................................................................................	2-2
		2.2.2	Register Attributes.................................................................................	2-3
		2.2.3 Reserved Bits Defined in Registers.......................................................		2-3
		2.2.4 Reserved or Undefined Register Locations...........................................		2-3
		2.2.5	Default Upon Reset ...............................................................................	2-3
		2.2.6	Consistency...........................................................................................	2-4
		2.2.7	GART Programming Region .................................................................	2-4
	2.3	I/O Mapped Registers ........................................................................................		2-4
		2.3.1 CONFIG_ADDRESS: Configuration Address Register .........................		2-4
		2.3.2 CONFIG_DATA: Configuration Data Register ......................................		2-5
	2.4	Error Handling Registers ....................................................................................		2-5
		2.4.1	SAC .......................................................................................................	2-5
		2.4.2	SDC.....................................................................................................	2-11
		2.4.3	MAC ....................................................................................................	2-21
		2.4.4	PXB .....................................................................................................	2-22
		2.4.5	GXB.....................................................................................................	2-24
		2.4.6	WXB ....................................................................................................	2-27
	2.5	Performance Monitor Registers........................................................................		2-30
		2.5.1	SAC .....................................................................................................	2-30
		2.5.2	SDC.....................................................................................................	2-34
		2.5.3	PXB .....................................................................................................	2-36
		2.5.4	GXB.....................................................................................................	2-38
		2.5.5	WXB ....................................................................................................	2-43
	2.6	Interrupt Related Registers ..............................................................................		2-44
		2.6.1	SAC .....................................................................................................	2-44
		2.6.2 PID PCI Memory-mapped Registers ...................................................		2-45
		2.6.3 PID Indirect Access Registers.............................................................		2-46

Intel® 460GX Chipset System Software Developer’s Manual iii