Register Descriptions

2.4.6.5FEPCIAL: PCI First Error Address/Command Log

Address Offset:

A5h–ADh

Size:

72 bits

Default Value:

000000000000000000h

Attribute:

Read/Write Clear,

Sticky

 

 

 

These registers record and latch the address/command information, sent or received, associated with a PCI Bus error for the first error detected.

Bits Description

71:68 reserved (0)

67:64 C/BE[3:0]63:32 AD[63:32]31:0 AD[31:0]2.4.6.6FEPCIDL: PCI First Error Data Log

Address Offset:

AFh – B3h

Size:

40 bits

Default Value:

0000000000h

Attribute:

Read/Write Clear,

Sticky

 

 

 

These registers record and latch the PCI information, sent or received, specifically associated with the PCI bus error for the first error detected. The recorded data contains the upper or lower AD and C/BE and PAR signals.

Bits Description

39:37 reserved (0)

36PAR

35:32 C/BE

31:0 AD

2.5Performance Monitor Registers

2.5.1SAC

2.5.1.1IT_MON_PMD_[0 to 5]: Internal Transaction Performance Monitor Data Register

Bus CBN, Device Number:

00h

Function:

2

Address Offset:

90-97h, 98-9Fh,

Size:

64 bits each

 

A0-A7h, A8-AFh,

 

 

 

B0-B7h, B8-BFh

 

 

Default Value:

0 each

Attribute:

Read/Write

Sticky:

No

Locked:

No

The value written to this address, loads the counter and is also saved in a reload register. Each counter can be configured to reload the data when it overflows.

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Intel® 460GX Chipset Software Developer’s Manual