5.6 Timing

5.6.3 Ultra DMA data transfer

Figures 5.11 through 5.20 define the timings associated with all phases of Ultra DMA bursts.

Table 5.23 contains the values for the timings for each of the Ultra DMA Modes.

5.6.3.1Initiating an Ultra DMA data in burst

5.6.3.2contains the values for the timings for each of the Ultra DMA Modes.

DMARQ

tUI

 

 

 

(device)

 

 

 

DMACK-

 

 

 

 

(host)

 

 

tFS

 

 

tACK

 

 

 

tENV

 

 

STOP

 

 

tZAD

 

(host)

tACK

 

 

 

 

tENV

tFS

 

HDMARDY-

 

 

 

 

(host)

 

 

tZAD

 

 

 

 

 

 

tZIORDY

 

tZFS

 

DSTROBE

 

 

tDZFS

 

(device)

 

 

 

 

tAZ

 

tVDS

tDVH

 

 

 

DD (15:0)

 

 

 

 

 

tACK

 

 

 

DA0,DA1,DA2,

 

 

 

 

CS0-,CS1-

 

 

 

 

 

Note:

 

 

 

The definitions for the STOP, HDMARDY-and DSTROBE signal lines are not in effect until DMARQ and DMACK- are asserted.

Figure 5.11 Initiating an Ultra DMA data in burst

C141-E218

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Fujitsu MHV2120AT, MHV2100AT, MHV2080AT, MHV2040AT, MHV2060AT Ultra DMA data transfer, Initiating an Ultra DMA data in burst