
Interface
*8 | Word 59: Transfer sector count currently set by READ/WRITE | |
|
| MULTIPLE command |
| Bits | Reserved |
| Bit 8: | '1' = Enable the multiple sector transfer |
| Bits | Transfer sector count currently set by READ/WRITE MULTIPLE |
|
| command without interrupt supports 2, 4, 8 and 16 sectors. |
*9 | Word 63: Multiword DMA transfer mode | |
| Bits | |
| Bit 10: | '1' = multiword DMA mode 2 is selected. |
| Bit 9: | '1' = multiword DMA mode 1 is selected. |
| Bit 8: | '1' = multiword DMA mode 0 is selected. |
| Bits | Reserved |
| Bit 2: | '1' = Multiword DMA mode 2, 1, and 0 supported (Bit 1 = 0 = '1') |
| Bit 1: | '1' = Multiword DMA mode 1, and 0 supported (Bit 0 = '1') |
| Bit 0: | '1' = Mode 0 |
*10 | Word 64: Advance PIO transfer mode support status | |
| Bits | Reserved |
| Bits | Advance PIO transfer mode |
| Bit 1: | '1' = Mode 4 supported |
| Bit 0: | '1' = Mode 3 supported |
*11 | WORD 75: X ' 001F ' (32) | |
*12 WORD 76 |
| |
| Bits | |
| Bit 10: | '1' = Supports the PHY event counter. |
| Bit 9: | '1' = Supports the Power Management initiation request from |
|
| the host system. |
| Bit 8: | '1' = Supports the Native command queueing. |
| Bits | Reserved |
| Bit 3: | Reserved for SATA |
| Bit 2: | '1' = Supports the |
| Bit 1: | '1' = Supports the |
Bit 0: Reserved