
Device Type Register
| base + 0216 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 
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| Write | 
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 | Undefined | 
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| Read | 
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 | Model Code | 
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Status/Control Register
| base + 0416 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 
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| Write | 
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 | Undefined | 
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 | X | X | X | TRG | DIR | IRQ | X | CRD | |||
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 | INT | 
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| Read | 
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 | Undefined | 
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 | 1 | 1 | 1 | BSY* | 1 | 1 | IRQ* | IRQ | |||
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 | EN* | 
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Scan Control Register
| base + 0616 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 
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| Write | 
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 | Undefined | 
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 | X | X | X | RST | CNT | IMM | DBS | CLR | |||
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 | PTR | EN | EN | EN | SCN | 
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| Read | 
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 | Undefined | 
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 | 1 | 1 | 1 | 1 | CNT | IMM | DBS | CLR | |||
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 | EN | EN | EN | SCN | 
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Scan Channel Delay Register
| base + 0816 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 
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| Write | 
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 | Undefined | 
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 | X | X | X | X | D3 | D2 | D1 | D0 | |||
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| Read | 
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 | Undefined | 
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 | 1 | 1 | 1 | 1 | D3 | D2 | D1 | D0 | |||
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Scan Channel Configuration Register
| base + 0A16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 
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| Write | VLD* | A_D* | B_D* | C1 | C0 | X | X | X | X | X | X | X | D3 | D2 | D1 | D0 | 
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| Read | 
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 | Undefined | 
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Direct Channel Configuration Register
| base + 0C16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 
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| Write | 
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 | Undefined | 
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 | X | X | X | X | D3 | D2 | D1 | D0 | |||
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| Read | 
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 | Undefined | 
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Direct Control Register
| base + 0E16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 
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| Write | 
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 | Undefined | 
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 | X | X | X | VLD* | A_D* | B_D* | C1 | C0 | |||
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| Read | 
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 | Undefined | 
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| Appendix B | HP E1351A/53A  | 
