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ports per HA and up to 16 HAs in the smallest family member of the DS8000 series, the DS8100, you can configure up to 64 FICON channel ports. This still provides 16 FICON channel paths to each single device, which is beyond what the zSeries Channel Subsystem provides with its limit of up to eight channel paths per device as a maximum.

			2 Gbps Fibre Channel ports
To host servers
			Fibre Channel	Fibre Channel
			Protocol Proc	Protocol Proc
Adapter		Adapter
Processor	Memory	Processor	PowerPC
		Storageserver
				HA
Adapter		Adapter

Figure 12-5 Host adapter with 4 Fibre Channel ports

The front end with the 2 Gbps ports scales up to 128 ports for a DS8300. This results in a theoretical aggregated host I/O bandwidth of 128 times 2 Gbps and outperforms an ESS by a factor of eight. The DS8100 still provides four times more bandwidth at the front end than an ESS.

12.3.4 POWER5 - Heart of the DS8000 dual cluster design

The DS8000 series incorporates the latest pSeries POWER5 processor technology. The actual processor used is an eServer p5 570 server, which scales from a 1-way to a 16-way SMP using standard 4U building blocks. The first two family members of the DS8000 series utilize two-way and four-way processor complexes. The following sections discuss configuration and performance aspects based on the two-way processor complexes used in the DS8100.

Among the most exciting capabilities the pSeries inherited from zSeries are the dynamic LPAR mode and the micro partitioning capability. This pSeries-based functionality has the potential to be exploited also in future disk storage server enhancements. For details on what the first steps with LPAR technology in the DS8000 look like see Chapter 3, “Storage system LPARs (Logical partitions)” on page 43.

Besides the self-healing features and advanced RAS attributes, the RIO-G structures provide a very high I/O bandwidth interconnect with DAs and HAs to provide system-wide balanced aggregated throughput from top to bottom. A simplified view is in Figure 12-6 on page 262. The smallest processor complex within a DS8100 is the POWER5 p570 two-way SMP processor complex. The dual-processor complex approach allows for concurrent microcode loads, transparent I/O failover and failback support, and redundant, hot-swapable components.

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