Intel CB60-BX, CB60-ZX Sdram RAS-to-CAS Delay, Sdram RAS Precharge Time, Sdram CAS Latency Time

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Award BIOS Setup Utility

SDRAM RAS-to-CAS Delay

This field allows you to insert a timing delay between the CAS and RAS strobe signals, used when DRAM is written to, read from, or refreshed. This field applies only when synchronous DRAM is installed in the system.

SDRAM RAS Precharge Time

If there is insufficient number of cycles for the RAS to accumulate its charge before DRAM refresh, the refresh may be incomplete and the DRAM may fail to retain data.

SDRAM CAS Latency Time

The default setting is 3 which is 3 clock cycles for the CAS latency.

DRAM Data Integrity Mode (CB60-BX only)

This field will appear only when you are using the CB60-BX system board which supports ECC. The ECC (Error Checking and Correction) function is supported only in x72 (72-bit) PC SDRAM DIMMs. If you are using x64 (64-bit) PC SDRAM DIMMs, set this field to Non-ECC.

Non-ECC Uses x64 PC SDRAM DIMM.

ECC This option allows the system to recover from memory failure. It detects single-bit and multiple-bit errors, then automatically corrects single-bit error.

System BIOS Cacheable

When this option is enabled, accesses to the system BIOS ROM addressed at F0000H-FFFFFH are cached, provided that the cache controller is enabled.The larger the range of the Cache RAM, the higher the efficiency of the system.

Video BIOS Cacheable

As with caching the system BIOS, enabling the Video BIOS cache will allow access to video BIOS addresssed at C0000H to C7FFFH to be cached, if the cache controller is also enabled.The larger the range of the Cache RAM, the faster the video performance.

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