Introduction

Figure 3. RSS Host with Bridge Mezzanine Block Diagram

 

 

Base CPU Board

Interboard

Interboard

Bridge Mezzanine

 

 

 

 

 

 

 

 

 

 

Connector

Connector

 

 

 

 

CPU/

 

 

 

 

 

 

 

 

 

Chipset

xMC

 

 

 

 

 

 

 

 

 

HC

 

 

Control/

Xreq

 

 

 

 

 

 

 

 

Status

 

 

 

 

 

Xreq

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI

Control/Status

 

 

 

 

 

 

 

 

CIC

Control

 

CIC

 

Control

 

PCI

 

 

 

 

 

 

 

 

Iso/Term

Clk.

Arb.

 

 

Arb.

Clk.

Iso/Term

 

 

CompactPCI J1/J2

 

 

CompactPCI J1/J2

 

 

 

Bus Segment A

 

 

 

Bus Segment B

2.2.3

Backplane

 

 

 

 

 

 

 

The RSS system backplane supports two CompactPCI buses accessible by both Redundant Hosts. In Active-Standby mode, the active processor board controls the buses (Active Host) and the standby processor board is isolated from the backplane (Drone mode). By using Active-Active- capable processor boards such as the ZT 5524, the system can be configured so that each processor board has access to one backplane bus (Cluster mode). The backplane has separate buses for active-to-standby processor board communication (COMM) and Host Controller functions. See Figure 4, “High-Availability System Backplane Architecture” on page 18 for an example of a typical High-Availability backplane.

High Availability Software for the Intel® NetStructureTM ZT 4901 Technical Product Specification

17

Page 17
Image 17
Intel ZT 4901 manual Backplane, RSS Host with Bridge Mezzanine Block Diagram