
Introduction
Figure 3. RSS Host with Bridge Mezzanine Block Diagram
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| Base CPU Board | Interboard | Interboard | Bridge Mezzanine |
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| Connector | Connector |
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| CPU/ |
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| Chipset | xMC |
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| HC |
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| Control/ | Xreq |
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| Status |
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| Xreq |
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| PCI | Control/Status |
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| CIC | Control |
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| PCI | |
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| Iso/Term | Clk. | Arb. |
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| Arb. | Clk. | Iso/Term |
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| CompactPCI J1/J2 |
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| CompactPCI J1/J2 | ||||
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| Bus Segment A |
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| Bus Segment B | ||
2.2.3 | Backplane |
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The RSS system backplane supports two CompactPCI buses accessible by both Redundant Hosts. In
High Availability Software for the Intel® NetStructureTM ZT 4901 Technical Product Specification | 17 |