Interphase Tech 4221 INDEX

INDEX

Numerics

82596 4, 81, 82

A

Abort ALL (AA) 79

Abort ANY (AN) 79

Abort Pending (AP) 81

Abort Report (AR) 80, 81

B

board ok (BOK) 57 BOK 57

C

dual 10BaseT daughter card 51 dual AUI daughter card 51 installing 52

single channel AUI/10BaseT daughter card 51

CC62 CE 63 CIB 74 CNA 57

Command Complete (CC) 62

Command Options 71, 79, 86, 88, 91, 94, 96 Command Queue Entry (CQE) 59, 60 Command Response Block (CRB) 56, 62, 74, 93 Command Response Block Valid (CRBV) 62 Command Response Status Word (CRSW) 62 Command Tag 60, 63

compatibility Eagle 53

Configuration Status Block (CSB) 56, 65 connectors

dual 10BaseT daughter card 49 dual AUI daughter card 50 Ethernet 101, 102, 104 RS232 101, 106

single channel AUI/10BaseT daughter card 48 VMEbus 101, 102

contiguous data allocation 54 Control Flags 94

Control MAC IOPB 80 Controller Error (CE) 63

Controller Initialization Block (CIB) 74 Controller Initialization Block Offset 73 Controller Panic 63

controller reset (RES) 58 Controller Reset (RST) 58 Controller Statistics Block 56 CPU core 5, 6

CQE 56, 59, 74, 88 CRB 56, 62, 76 CRBV 62, 76 CRSW 62

customer service 7

D

Data Valid Indicator 97 daughter card

dual 10BaseT 8, 49, 99 dual AUI 8, 50, 99 single AUI/10BaseT 8

single channel AUI/10BaseT 48, 99 DB15 101, 104

Default Node Address 85 DIR 72

Direction bit (DIR) 72

Disable multiple completion (DMC) 88, 91 DMA Burst Count 75

DMA Control Word 80 DMA engine 4

DMA Transfer Control Word 61, 71, 88 DMC 88, 91

E

Electrostatic Discharge (ESD) 7 EM 81

Enable Multiple Completions (MEN) 94 Enable/Disable MAC (EM) 81

ER 63 error

abort pending 107 bus 107

illegal MAC option 107 illegal option 107 illegal parameter 107 link status 107

network interface not initialized 107 transmit 107

VMEbus 107 Error (ER) 63

Error Completion Level / Vector 71 Ethernet MAC Addresses 66 Ethernet Physical Node Addresses 75

109

Contents

Page Page Copyright Notice Interphase Corporation Disclaimer For Assistance Trademark Acknowledgments TABLE OF CONTENTS Page Page Page LIST OF FIGURES Page LIST OF TABLES Page INTRODUCTION Page Page DMA Engine VMEbus Drivers And Receivers Page Page HARDWARE INSTALLATION Product Page Page Page Page Page Step 1. Visual Inspection Step 2. Fuse And Diagnostic LEDs Fuse Diagnostic LEDs Designator Board Status LEDs POST Mode: Hex Code Diagnostic Definition CAUTION J5 FLASH0 J9 +12 VOLTS Flash Programming Protect: J12 VME Bus Grant: J13 Firmware Option Jumpers: J14 Firmware Option Jumpers: J15 Firmware Option Jumpers / Secondary Short I/O Size: J16 Primary Short I/O Size / Reset Enable: J17 Secondary Channel Address Modifiers: J18 Primary Channel Address Modifiers: J19, J20, J21 & J22 Primary Short I/O Base Address: NOTE Page Page Page Page Page Page Page Page Page Page J23, J24, J25 & J26 Secondary Short I/O Address: Page Page Page Page Page Page Page Page Page Page Page Page Page Step 4. Set Daughter Card Jumpers And Terminations Ethernet Single Channel AUI/10BaseT Daughter Card COMPONENT SIDE Dual Channel 10BaseT Ethernet Daughter Card Ethernet Dual Channel AUI Daughter Card Step 5. Power Off System CAUTION Step 6. Cabling Procedure Note: RS232 Connectors And Cables Installing The Cable(s) And Board MACSI HOST INTERFACE Field Offset Contiguous Data Allocation Page Page Master Status Register (MSR) Master Control Register (MCR) Queue Entry Control Register (QECR) IOPB Address Host Address Offboard Transfer Length Command Response Status Word (CRSW) IOPB Length Port This field is not valid for transmits Transfer Count This field is not valid for transmits Product Code Product Variation Firmware Revision Level Firmware Revision Date Ethernet MAC Addresses (Ports 0 - 3) Page Transmit Commands Submitted Transmit DMA Completions Transmit 82596 Completions Successful Transmits Failed Transmits Transmit Completions Posted to Host Receive Commands Submitted Receives Dropped - No Pending Receive Command Receive 82596 Completions Failed Receives Page Normal Completion Level / Vector Error Completion Level / Vector Page Controller Initialization Block Offset Number of CQE Entries Special Network Options Ethernet Physical Node Addresses Interrupt Levels and Vectors DMA Burst Count Offboard CRB DMA Transfer Control Word Offboard CRB host address Page Page Page Buffer address Transfer size MAC status/control Intel 82596 Status/Control – Transmit Functions Intel 82596 Status/Control – Receive Functions Page MAC returned information Page Page Page Page Number of Elements Total transfer count Element transfer count Page Buffer Address Maximum / Actual Transfer Size Packet Type / Length Field Source Address Disable Multiple Completion Control Flags Group Interrupt Level / Vector Minimum Group Count Maximum Group Count Page Host Memory Buffer Address Max Transfer Size Timer Interval Data Valid Indicator Port Indicator Transmits Submitted Transmits Completed Transmits Failed Collisions Receives Submitted Receives Returned Receives Dropped (Resources) APPENDIX A SPECIFICATIONS NOTE Page APPENDIX B CONNECTOR PINOUTS AND CABLING P1 Connector P2 Connector Row B Only Version 10BaseT Connector Signals AUI Connector Signals Page APPENDIX C ERROR CODES Page INDEX