Chapter 3 - MACSI Host Interface

The Master Command Entry (MCE) and Command Queue Entries (CQE) are used to queue commands from the host to the controller. A Command Queue Entry (in either the CQE or MCE) is a 12-byte block containing all of the information needed for the 4221 to locate and execute a command issued by the host. Control commands, such as Initialize Controller, are submitted through the MCE. Transmit and Receive commands are submitted through the CQE.

Commands issued by the host are named IO Parameter Blocks, or IOPBs, and can either be located in the controller’s Short I/O memory, in which case they are issued via an onboard CQE, or located in host system memory, in which the host uses an offboard CQE, and the controller DMA transfers the command in prior to execution. If located in onboard space, these IOPBs are located from the end of the last Command Queue Entry to the beginning of the Command Response Block.

The Command Response Block (CRB) and Returned IOPB areas are where the controller posts back status about completed commands to the host. Since interrupt bandwidth is the bottleneck resource in many network applications, the 4221 provides a Multiple Completion facility in which multiple commands can be returned to the host with a single interrupt, which uses not only the Returned IOPB space, but the entire rest of the Short I/O space.

Finally, the Configuration Status Block contains configuration information such as the firmware revision level. Typically, this is used only at system initialization time, and is overwritten by multiple completion commands during routine operation.

The Controller Statistics Block is a hold over from the old Eagle host interface. It is only updated on single channel daughtercards. A special command has replaced the function provided here, which allows more statistics to be reported for multiple ports. Again, as in the Configuration Status Block area, the Controller Statistics Block may be overwritten by multiple completion commands during routine operation.

NOTE:

The short I/O interface of the 4221 Condor is accessed through the secondary short I/O space only. Refer to “J23, J24, J25 & J26 Secondary Short I/O Address:” on page 33 for secondary short I/O address settings.

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