Interphase Tech 4221 52

Chapter 2 - Hardware Installation

Table 2-14. Secondary Base Address For 512 Byte Short I/O (Continued

ADDRESS

J23 PIN SETTINGS

J24, J25, J26 PIN SETTINGS

15-16

13-14

11-12

9-10

7-8

5-6

3-4

1-2

J24

J25

J26

F000

F200

F400

F600

F800

FA00

FC00

FE00

Contents

Page Page Copyright Notice Interphase Corporation Disclaimer For Assistance Trademark Acknowledgments TABLE OF CONTENTS Page Page Page LIST OF FIGURES Page LIST OF TABLES Page INTRODUCTION Page Page DMA Engine VMEbus Drivers And Receivers Page Page HARDWARE INSTALLATION Product Page Page Page Page Page Step 1. Visual Inspection Step 2. Fuse And Diagnostic LEDs Fuse Diagnostic LEDs Designator Board Status LEDs POST Mode: Hex Code Diagnostic Definition CAUTION J5 FLASH0 J9 +12 VOLTS Flash Programming Protect: J12 VME Bus Grant: J13 Firmware Option Jumpers: J14 Firmware Option Jumpers: J15 Firmware Option Jumpers / Secondary Short I/O Size: J16 Primary Short I/O Size / Reset Enable: J17 Secondary Channel Address Modifiers: J18 Primary Channel Address Modifiers: J19, J20, J21 & J22 Primary Short I/O Base Address: NOTE Page Page Page Page Page Page Page Page Page Page J23, J24, J25 & J26 Secondary Short I/O Address: Page Page Page Page Page Page Page Page Page Page Page Page Page Step 4. Set Daughter Card Jumpers And Terminations Ethernet Single Channel AUI/10BaseT Daughter Card COMPONENT SIDE Dual Channel 10BaseT Ethernet Daughter Card Ethernet Dual Channel AUI Daughter Card Step 5. Power Off System CAUTION Step 6. Cabling Procedure Note: RS232 Connectors And Cables Installing The Cable(s) And Board MACSI HOST INTERFACE Field Offset Contiguous Data Allocation Page Page Master Status Register (MSR) Master Control Register (MCR) Queue Entry Control Register (QECR) IOPB Address Host Address Offboard Transfer Length Command Response Status Word (CRSW) IOPB Length Port This field is not valid for transmits Transfer Count This field is not valid for transmits Product Code Product Variation Firmware Revision Level Firmware Revision Date Ethernet MAC Addresses (Ports 0 - 3) Page Transmit Commands Submitted Transmit DMA Completions Transmit 82596 Completions Successful Transmits Failed Transmits Transmit Completions Posted to Host Receive Commands Submitted Receives Dropped - No Pending Receive Command Receive 82596 Completions Failed Receives Page Normal Completion Level / Vector Error Completion Level / Vector Page Controller Initialization Block Offset Number of CQE Entries Special Network Options Ethernet Physical Node Addresses Interrupt Levels and Vectors DMA Burst Count Offboard CRB DMA Transfer Control Word Offboard CRB host address Page Page Page Buffer address Transfer size MAC status/control Intel 82596 Status/Control – Transmit Functions Intel 82596 Status/Control – Receive Functions Page MAC returned information Page Page Page Page Number of Elements Total transfer count Element transfer count Page Buffer Address Maximum / Actual Transfer Size Packet Type / Length Field Source Address Disable Multiple Completion Control Flags Group Interrupt Level / Vector Minimum Group Count Maximum Group Count Page Host Memory Buffer Address Max Transfer Size Timer Interval Data Valid Indicator Port Indicator Transmits Submitted Transmits Completed Transmits Failed Collisions Receives Submitted Receives Returned Receives Dropped (Resources) APPENDIX A SPECIFICATIONS NOTE Page APPENDIX B CONNECTOR PINOUTS AND CABLING P1 Connector P2 Connector Row B Only Version 10BaseT Connector Signals AUI Connector Signals Page APPENDIX C ERROR CODES Page INDEX